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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Leverage cache replacement policy in multicore processors

Leverage cache replacement policy in multicore processors

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IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Marius Geanta Lavinia Ghica Nicolae Tapus Bucharest Romania “Politehnica” University of Bucharest Bucharest Romania Computer Science Departament “Politehnica” University of Bucharest Bucharest Romania

ISBN: (纸本)9781509039005

Computer hardware is currently moving towards heavily parallelized architectures with multiprocessors, multicore and chip multithreaded designs. Cache memory, the fastest component of the memory hierarchy, adapts to this new kind of parallel systems in order to provide the promised performance increase. Current cache designs have limitations that can be transformed into optimization opportunities both in hardware and software. this paper provides a detailed research of cache performance in multicore processors, considering critical hardware aspects. A new solution is proposed to improve the current performance: an optimized replacement policy for the shared cache level. From experiments run on four and eight core setups in a multicore simulator, the proposed enhancements achieve up to 30% execution speed increase over the default setup.

关键词： Multicore processing Program processors Hardware throughput Approximation algorithms Electronics packaging

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Application task and data placement in embedded many-core NUMA architectures 13

Application task and data placement in embedded many-core NU...

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10th Workshop on Optimizations for DSP and Embedded Systems, ODES 2013 - In Conjunction with international Symposium on Code Generation and Optimization, CGO 2013

作者： Viring, Karl Lee, Sangheon Cho, Yeongon Ryu, Soojung Egger, Bernhard School of Computer Science and Engineering Seoul National University Korea Republic of Samsung Electronics Samsung Advanced Institute of Technology Korea Republic of

ISBN: (纸本)9781450319058

the advent of many-core chips in the embedded world imposes new challenges to programmers. One of the most important challenges to achieve optimal performance is that the variance in memory access time depending on the issuing core and the location of the data has to be taken into consideration in the already complex environment of parallel applications. In this paper we seek efficient ways of implementing dynamic task and data placement for embedded many-core systems that exhibit NUMA. Achieving a high affinity between a task and its data is desirable to minimize memory access cost and program execution time. this research was carried out using a many-core MPSoC FPGA prototype from Samsung. the MPSoC comprises 16 reconfigurable processors, global SDRAM and distributed scratchpad memory. Since no message passing interface or API's such as OpenMP is available for the Samsung 16-SRP, this paper focuses on optimizations in the application layer. To gain insight into memory performance, a series of micro benchmarks has been carried out. these benchmarks aim at discovering NUMA behavior, memory hierarchy latencies, architecture symmetry, DMA-transfer overhead and congestion. Accessing the SDRAM exhibits NUMA factors up to 1.45, however, the most important factor for achieving high performance is to minimize congestion in the NoC and at the memory controllers. We have applied these findings to two real-world imaging applications, image-blurring and Seeded Region Growing (SRG). the base cases for both applications are parallelized for 16 cores. For image burring, we achieve a 2.75- to 3-fold speedup by distributing the image data to the four SDRAMs and statically assigning the work items to the cores closest to the data. Depending on input image, the SRG application shows a 1.4- to 1.5-fold speedup compared to the base case by applying dynamic work load balancing using hierarchical queues and work-stealing. the results emphasize the importance of considering the underlying

关键词： Message passing

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Power-Performance Comparison of Single-Task Driven Many-Cores

Power-Performance Comparison of Single-Task Driven Many-Core...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Fuat Keceli Tali Moreshet Uzi Vishkin Department of Electrical and Computer Engineering University of Maryland USA Department of Engineering Swarthmore College USA

Many-cores, processors with 100s of cores, are becoming increasingly popular in general-purpose computing, yet power is a limiting factor in their performance. In this paper, we compare the power and performance of two design points in the many-core processor domain. the XMT general-purpose processor provides significant runtime advantage on irregular parallel programs (e.g., graph algorithms). this was previously demonstrated and tied to its architecture choices and ease-of-programming. In contrast, current commercial GPUs excel at regular parallel programs that require high processing capability. In this work, we set the power envelope as a constraint and evaluate an envisioned 1024-core XMT processor against an NVIDIA GTX280 GPU considering various scenarios for estimating the power of the XMT chip. Even under worst-case assumptions and scenarios, simulations show that the XMT processor sustains its advantage over the GPU on irregular parallel programs, while not falling significantly behind on regular programs. the total energy spent per benchmark fits a similar pattern. Given that the two architectures target different types of parallelism, a future system can potentially utilize an XMT chip and a GPU chip in complementary roles.

关键词： Benchmark testing Graphics processing unit Computer architecture Temperature measurement Clocks Random access memory

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Towards Adapting parallel Programs to Different Platforms: Identifying Interaction Patterns

Towards Adapting Parallel Programs to Different Platforms: I...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Bogdan Florin Cornea Jaroslaw Slawinski Julien Bourgeois Vaidy Sunderam Emory University Atlanta GA US FEMTO-ST Inst. UFC Besançon France

Modern parallel computing platforms exhibit substantial variation in communication performance between on-socket, on-node and inter-rack locations. When application interaction patterns are irregular, communication-aware process placement on such platforms can be critical for overall runtime. Understanding program interaction patterns can be valuable in order to minimize the impact of capacity variations in communications parameters. Such knowledge can also be useful in selecting the best execution platform from the available options. In this paper we propose an approach based on source code analysis which identifies parallel application communication patterns such as star, ring, mesh, or torus. Our implementation based on ROSE framework was tested on various parallel programs that exhibit different communication patterns. We present the accuracy as well as the limitations of our static identification approach. We envisage augmenting our approach with trace information from pilot runs and best effort approaches to determine a process interaction graph.

关键词： Topology Network topology parallel processing Computer architecture Blood vessels Runtime Object recognition

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parallel Dense Gauss-Seidel Algorithm on Many-Core Processors

Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Hadrien Courtecuisse Jérémie Allard INRIA Lille Nord Europe France

the Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing methods, taking advantage of recent many-cores architectures offering fast synchronization primitives. Experimental results on both multi-core CPUs and recent GPUs show that our proposed method is able to fully exploit the available units, whereas trivial parallel algorithms often fail. this method is illustrated by an application in medical intervention planning, where it is used to solve a linear complementary problem (LCP) expressing the contacts applied to a deformable body.

关键词： Gaussian processes High performance computing parallel processing Concurrent computing Jacobian matrices Computer architecture Equations Pervasive computing Linear systems Europe

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Compute Pairwise Manhattan Distance and Pearson Correlation Coefficient of Data Points with GPU

Compute Pairwise Manhattan Distance and Pearson Correlation ...

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ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing (SNPD)

作者： Dar-Jen Chang Ahmed H. Desoky Ming Ouyang Eric C. Rouchka Computer Engineering & Computer Science Department University of Louisville Louisville KY USA

Graphics processing units (GPUs) are powerful computational devices tailored towards the needs of the 3-D gaming industry for high-performance, real-time graphics engines. Nvidia Corporation released a new generation of GPUs designed for general-purpose computing in 2006, and it released a GPU programming language called CUDA in 2007. the DNA microarray technology is a high throughput tool for assaying mRNA abundance in cell samples. In data analysis, scientists often apply hierarchical clustering of the genes, where a fundamental operation is to calculate all pairwise distances. If there are n genes, it takes O(n^2) time. In this work, GPUs and the CUDA language are used to calculate pairwise distances. For Manhattan distance, GPU/CUDA achieves a 40 to 90 times speed-up compared to the central processing unit implementation; for Pearson correlation coefficient, the speed-up is 28 to 38 times.

关键词： Sequences Distributed computing Central processing Unit Concurrent computing Power engineering computing DNA Bioinformatics Computer networks Data analysis Graphics

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Efficient implementation of 3780-point FFT on a 16-core processor

Efficient implementation of 3780-point FFT on a 16-core proc...

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international conference on ASIC

作者： Haofan Yang Kedong Chen Shengqiong Xie Ming-e Jing Zhiyi Yu Xiaoyang Zeng State Key Laboratory of ASIC & System Fudan University Shanghai China Shanghai University of Engineering Science

the 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.

关键词： parallel processing Pipelines Algorithm design and analysis Discrete Fourier transforms Multicore processing Multimedia communication Standards

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Marıa del Carmen Calatrava Moreno thomas Auzinger Technische Universitat Wien Wien Wien AT Institute of Computer Graphics and Algorithms Vienna University of Technology Vienna Austria

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing units Hardware Computer architecture Graphics Instruction sets Computational modeling Semiconductor optical amplifiers

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Convergence throughput gain in a unified parallel turbo receiver

Convergence throughput gain in a unified parallel turbo rece...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Atif Raza Jafri Amer Baghdadi CESAT Islamabad Pakistan TELECOM Bretagne Brest France

ISBN: (纸本)9781467344258

In pursuit of bringing high end applications on radio platforms, recent and evolving wireless standards impose stringent requirements in the shape of high throughputs, error rate performance close to theoretical limits and multi mode transmissions to efficiently use bandwidth in different channel conditions. In the presence of these requirements, the designer comes across contradicting requirements. In fact, in order to handle error rate performance the iterative (Turbo) processing (Turbo/LDPC decoding, Turbo demodulation and Turbo Equalization) is common implementation practice in baseband receivers. However, this creates bottleneck in achieving imposed throughputs. In this scenario, parallelism study and resulting throughput gains while keeping same error rate convergence, provides the designer concrete results to establish compromise among design constraints. In this paper, first of all three level of parallelism study is presented on turbo decoding, turbo demodulation and MIMO turbo equalization. To aid the designer in taking decision during the design, mathematical expressions for throughput gain in unified parallel turbo receiver are provided. throughput gain for different system scenarios are computed by using system parameters and simulation results in derived expressions.

关键词： Decoding parallel processing Vectors throughput Receivers Equalizers MIMO

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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

VLSI-based parallel architecture for block-matching motion e...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Donglai Xu J. Bentley School of Science and Technology University of Teesside Middlesbrough UK

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

关键词： parallel architectures Motion estimation Video coding Computer architecture Very large scale integration Field programmable gate arrays Circuits Costs Pipelines Silicon

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