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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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High Performance Global Illumination on Multi-core architectures

High Performance Global Illumination on Multi-core Architect...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Emilio J. Padrón Margarita Amor Montserrat Bóo Ramón Doallo Dept. of Electronics and Systems Univ. A Coruña A Coruña Spain Dept. of Electronic and Computer Eng. Univ. Santiago de Compostela Santiago de Compostela Spain

Physically-based illumination is an essential factor for realistic rendering. In this context, hierarchical radiosity is one of the most accurate global illumination methods. One of the key features of the radiosity approach is that it obtains view-independent global illumination results. Unfortunately, global illumination has high computational and memory requirements, and hierarchical radiosity, though more efficient than other radiosity solutions, is not an exception. the progressive popularization of multiprocessor and multi-core processor systems makes the design and implementation of efficient parallel algorithms an appealing alternative in this field. In this paper we present a novel parallel radiosity method addressing the hierarchical radiosity computation on current homogeneous multi-core environments. One of the main contributions of our work is the use of different tasks to exploit the independent interactions among the geometric elements in the scene. Our parallel solution leads to a versatile radiosity implementation that takes advantage of the multiple computational resources in the system, such as multi-core processors and SMT (simultaneous multithreading) capabilities. Good results in terms of performance have been achieved.

关键词： Lighting Concurrent computing Multicore processing Layout Surface-mount technology Distributed computing Multithreading Proposals Processor scheduling Computer architecture

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Scalable and parallel Implementation of a Financial Application on a GPU: With Focus on Out-of-Core Case

Scalable and Parallel Implementation of a Financial Applicat...

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international conference on Computer and Information Technology (CIT)

作者： Myungho Lee Jin-hong Jeon Joonsuk Kim Joonhyun Song Department of Computer Science and Engineering Myoneji University Yongin si Gyeonggi South Korea

the architecture of the latest Graphic processing Unit (GPU) consists of a number of uniform programmable units integrated on the same chip, which facilitate the general-purpose computing beyond the graphic processing. With the multiple programmable units executing in parallel, the latest GPU shows superior performance for many non-graphic applications. Furthermore, programmers can have a direct control on the GPU pipeline using easy-to-use parallel programming environments. these advances in hardware and software make General-Purpose GPU computing (GPGPU) widespread. In this paper, we parallelize a computationally demanding financial application and optimize its performance on a latest GPU. We also analyze the performance results compared with those obtained using CPU only. Experimental results show that GPU can achieve a superior performance, greater than 190x, compared with the CPU-only case when the data fits in the graphic memory. We also address the performance issue in the out-of-core case where the data cannot fit in the device memory on the GPU. In such a case, by using streaming technique helps make up the performance gap lost due to data transfer overhead from the CPU side to the GPU DRAM.

关键词： Graphics processing unit Monte Carlo methods Instruction sets Computational modeling Kernel Arrays Random variables

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Massive efficiencies to be realized through GPU computations in finite element optimization: the promises and observations

Massive efficiencies to be realized through GPU computations...

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international conference on Industrial and Information Systems, ICIIS

作者： S. Ratnajeevan H. Hoole Election Commission Sarana Mawatha Rajagiriya 10107 Sri Lanka

In finite element optimization, the computational load limits the size of problem that can be solved. Finite element computation involves the solution of large matrix equations. then optimization requires several such equations to be solved. parallelization has been the preferred route to overcome this problem but was again limited by the cost of computers and the number of processors available. the graphics processing unit (GPU) on a PC provides a means of implementing the massive computations on numerous parallel threads cheaply on PCs. the purpose of this is to review finite element matrix equation solution on the GPU and point out areas where further investigation is warranted. Our intention is to direct computational research and computer architecture development so that we may use the GPU better for more effective computational parallelization in finite element field computation.

关键词： Graphics processing units Finite element analysis Refining Acceleration

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FPGA-based Acceleration of Deep Neural Networks Using High Level Method

FPGA-based Acceleration of Deep Neural Networks Using High L...

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Lei Liu Jianlu Luo Xiaoyan Deng Sikun Li Department of Electronics Officers College Of Chinese Armed Police Force Cheng Du China School of Computer Science National University of Defense Technology Chang Sha China

ISBN: (纸本)9781467394741

Deep neural network (DNN) is becoming more and more applied in data center applications such as speech recognition, image search, etc. However, the training in DNN is very time-consuming because of its deep structure. this paper presents FPGA-based acceleration of deep neural networks using a high level method and proposes a parallel optimizing strategy using the Kintex-7 FPGA board's features. Experimental results show that it can increase the utilization of FPGA computation units with low mini-batch size and reduce the transfer cost effectively. the optimized algorithm achieves up to 17.65x higher performance than CPU.

关键词： Training Field programmable gate arrays Acceleration Speech recognition Graphics processing units Biological neural networks

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Cognitive information processing based on a parallel processor

Cognitive information processing based on a parallel process...

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international conference on Digital Technologies (DT)

作者： Nikolai L. Verenik Alexey I. Girel Yerzhan N. Seitkulov Mikhail M. Tatur Hanna P. Razhkova Belarusian State University of Informatics and Radioelectronics Minsk Belarus L.N. Gumilyov Eurasian National University Kazakhstan Astana Intellectual Processors Ltd. Minsk Belarus

In this paper we consider the cognitive process as a set of different tasks. In particular tasks of clustering, classification and search of association. Described the parameters of similarity of these tasks, hypothesized the possibility of creating a unified methodology for cognitive systems. Shown the possible original architecture of the system, its description, command and data formats, the principles of operation. Describes the implementation of a system model for the GPU.

关键词： Hardware Computer architecture Computers Algorithm design and analysis Semantics Process control Graphics processing units

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Adaptive parallel Interval Global Optimization algorithms Based on their Performance for Non-dedicated Multicore architectures

Adaptive Parallel Interval Global Optimization Algorithms Ba...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： J.F. Sanjuan Estrada L.G. Casado I. García Universidad de Almeria Almeria AndalucÃa ES Department of Computer Architecture and Electronics University of Almeria Almería Spain Department of Computer Architecture University of Mälaga Mälaga Spain

Branch and Bound (B&B) algorithms are highly parallelizable but they are irregular and dynamic load balancing techniques have been used to avoid idle processors. In previous work, authors use a dynamic number of threads at run time, which depends on the measured performance of the application for just one interval B&B algorithm running on the system. In this way, load balancing is achieved by thread generation decisions. In this work, we extend the study of these models to non-dedicated systems. In order to have a controlled test bed and comparable results, several instances of the interval global optimization algorithm are executed in the system, with the same model and problem to solve. therefore, a non-dedicated system is simulated because the execution of one application affects the execution of the other instances. this paper discusses different methods and models to decide when a thread should be created. Experiments show which of the proposed methods performs best in terms of maximum running time per application, using the fewest running threads. Following this parallel programming methodology, which is well suited for other B&B codes, applications can adapt their parallelism level to their performance and load of the system(at run time). this work represents a step forward towards increasing the performance of parallel algorithm running in non-dedicated and heterogeneous systems. the adaptive model discussed in this work is able to reduce the overall execution time for a set of instances of the same application running simultaneously. It also exempts the user from specifying the number of threads each application should use.

关键词： Instruction sets Kernel Computational modeling Adaptation model Load modeling parallel processing

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Implementation of a parallel graph partition algorithm to speed up BSP computing

Implementation of a parallel graph partition algorithm to sp...

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the 2014 10th international conference on Natural Computation (ICNC 2014) and the 2014 11th international conference on Fuzzy Systems and Knowledge Discovery (FSKD 2014)(第十届自然计算和第十一届模糊系统与知识发现国际会议)

作者： Shengmei Luo Lixia Liu Hongxu Wang Yang Liu Bin Wu Department of Computer Science and Technology Tsinghua University Beijing 100084 P. R. China Zhongxing Telecom Equipment Corporation Nanjing 210012 P. R. China Beijing University of Posts and Telecommunications Beijing 100876 P. R. China

ISBN: (纸本)9781479951499

the processing and mining information in large scale graph data have proven to be *** bulk synchronous parallel(BSP)computing model is suitable for this *** this paper,we implement the multi-level step-wise partitioning(MSP)algorithm in BSP programming model,and replace the original graph partition *** results on both experimental data and real world data proved this improvement achieved better data locality,reduced communication between work nodes,and it made a better performance than the original method.

关键词： complex network MapReduce BSP HAMA graph partition

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An Efficient Subband Method for Wideband Adaptive Beamforming

An Efficient Subband Method for Wideband Adaptive Beamformin...

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international conference on Advanced Communication Technology (ICACT)

作者： Longyang Huang Bin Shen Mengxing Li Zemin Liu Telecommunication Engineering School Beijing University of Posts and Telecommunications Beijing China Telecommunication Engineering Laboratory Graduate School of Information Technology and Telecommunications Inha University Incheon South Korea

An efficient subband adaptive beamformer with perfect reconstruction general parameter filter banks (GPFB) for wideband array antenna is proposed in this paper, which is used to enhance performance of suppressing the interference and accelerate convergence speed of weights. Instead of the conventional FFT filter banks, GPFB are utilized to partition the frequency band into several subbands without aliasing between them. With subbands running at downsampling and in manner of parallel, the loads of computational processing costs, compared with traditional fullband methods, can be alleviated. Deep suppression of the interference and convergence speed of weights are also improved.

关键词： Wideband Array signal processing Filter bank Broadband antennas Adaptive arrays Interference suppression Convergence Antenna arrays Acceleration Frequency

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Multi-UPF Traffic Prediction of 5G Core Network With Multi-Task Learning and Multi-core parallel Computing

Multi-UPF Traffic Prediction of 5G Core Network With Multi-T...

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international conference on Computer and Communications (ICCC)

作者： Yonghe Su Hongbing Ma Bin Chen Zhanyu Ma Tian Wang Di Ge Zhi Li Shifang Wang China United Network Communications Group Corporation Limited Beijing University of Posts and Telecommunications Beijing China

ISBN: (数字)9798331507077

ISBN: (纸本)9798331507084

Traffic prediction has become a key aspect of 5G core network management. However, predicting traffic for multiple User Plane Functions (Multi-UPF) has received limited attention. To achieve effective and efficient forecasting for Multi-UPF traffic with machine learning, this study proposes a framework combining multi-task learning and multi-core parallel computing. Firstly, the time-series traffic data of Multi-UPF is concatenated to form the input feature. then, Random Forest algorithm is used as the backbone of the multi-task learning-based prediction model, which is able to predict the traffic of each UPF simultaneously. Finally, the computation of the multi-task learning model is further accelerated through multi-core parallel processing. Experimental results demonstrate that the proposed multi-task learning approach outperforms single-task learning method in the accuracy of each UPF traffic prediction. Furthermore, the use of multi-core parallel computing enhances the prediction speed significantly.

关键词： Learning systems Accuracy 5G mobile communication Multicore processing Computational modeling parallel processing Predictive models Multitasking Prediction algorithms Random forests

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Optimized Belief Propagation Algorithm onto Embedded Multi and Many-Core Systems for Stereo Matching

Optimized Belief Propagation Algorithm onto Embedded Multi a...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Jean-François Nezan Alexandre Mercat Patrice Delmas Georgy Gimelfarb INSA Rennes UMR Rennes France The University of Auckland Auckland CBD New Zealand The University of Auckland Auckland Auckland NZ

Stereo matching techniques aim at reconstructing disparity maps from a pair of images. the use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. Local stereo matching algorithms are efficiently implemented on GPU and DSP. this paper presents the optimization of the One Dimension Belief Propagation (BP-1D) algorithm. BP-1D is faster than previous algorithms on monocore DSP and its implementation onto multicore DSPs is straightforward. BP-1D implemented on multicore embedded platforms out-performs previous stereo matching implementations reaching real-time performances for resolutions up to 1080p with a 10 Watts power consumption.

关键词： Digital signal processing Optimization Embedded systems VLIW Memory management Multicore processing

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