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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Mapping OpenMP Concepts to the Stream Programming Model

Mapping OpenMP Concepts to the Stream Programming Model

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the 5th international conference on Computer Science & Education(第五届国际计算机新技术与教育学术研讨会 ICCSE'10)

作者： Tao Tang Yisong Lin Xiaoguang Ren National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multithread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. the transformation between the two models has attracted much attention from the research community, since it is the foundation of porting programs between the two architectures. Most related researches focus on the efficiency of porting existing parallel programs to the new architectures such as GPUs. Very few of these studies, however, focus on the portative problem systematically, namely, what kind of parallel programs can be or should be transplanted into stream programs and mapped to run on the stream processors. In this paper, we study the mapping relationship of parallel mechanism in OpenMP to the stream programming model, and point out those parallel mechanisms in OpenMP that are infeasible or undesirable for stream programs. By analyzing two typical benchmarks, we draw the conclusion that a majority of scientific applications are suitable to be mapped to the stream programming model. Our conclusion effectively validates the idea of accelerating scientific applications with the stream processors.

关键词： OpenMP:stream programming model:parallel mechanism:mapping

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Accelerating Physical Simulations from a Multicomponent Lattice Boltzmann Method on a Single-Node Multi-GPU Architecture

Accelerating Physical Simulations from a Multicomponent Latt...

引用

international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Julien Duchateau François Rousselle Nicolas Maquignon Gilles Roussel Christophe Renaud Laboratoire d'Informatique Signal Image de la Côte d'Opale Université du Littoral Côte d'Opale Calais France

In this paper, we introduce an efficient method to accelerate flow simulations for an isothermal multiphase and multicomponent (MPMC) Lattice Boltzmann method (LBM) on a single-node multi-GPU architecture. Our objective is to propose an efficient way to improve performance of multiphase and multicomponent Lattice Boltzmann simulations by the use of Nvidia GPUDirect technology and Peer-to-Peer (P2P) data transfers. Optimization of Peer-to-Peer communications is also studied in this work by the use of a clustering algorithm. Several simulations are shown and performance is discussed in order to validate the method.

关键词： Computational modeling Peer-to-peer computing Lattice Boltzmann methods Graphics processing units Mathematical model Data models Data transfer

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Robustness of parallel multi-rate A/D converters to anti-aliasing filter non-idealities

Robustness of parallel multi-rate A/D converters to anti-ali...

引用

Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Caroline Lelandais-Perrault Morgan Roger SupÉlec Department of Signal Processing & Electronic Systems France

Any digitization system must be preceded by an anti-aliasing filter. For wideband high frequency applications, parallel multi-rate conversion systems such as time-interleaved or hybrid filter bank analog-to-digital converters (resp. TI-ADC or HFB) are attractive solutions. this paper compares the robustness of both techniques with respect to non-idealities of the anti-aliasing filter (AAF). theoretical results show that the signal-to-noise ratio (SNR) degradation due to out-of-band signals is lesser for HFBs than for TI-ADCs, provided that the analysis filters of the HFB are selective enough. Simulation results show that this is the case even for low-order analysis filters in the case of a four-channel HFB.

关键词： Signal to noise ratio Attenuation Quantization Degradation Frequency conversion Analytical models

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Time Efficient Dual-Field Unit for Cryptography-Related processing

Time Efficient Dual-Field Unit for Cryptography-Related Proc...

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16th IFIP WG 10 5 IEEE international conference on Very Large Scale Integration (VLSI-SoC 2008)

作者： Cilardo, Alessandro Mazzocca, Nicola Univ Naples Federico II Dipartimento Informat & Sistemist I-80125 Naples Italy

ISBN: (纸本)9783642122668

Computational demanding public key cryptographic algorithms, such as Rivest-Shamir-Adlernan (RSA) and Elliptic Curve (EC) cryptosystems, are critically dependent on modular multiplication for their performance. Modular multiplication used in cryptography may be performed in two different algebraic structures, namely GF(N) and GF (2(n)), which normally require distinct hardware solutions for speeding up performance. For both fields, Montgomery multiplication is the most widely adopted solution, as it enables efficient hardware implementations, provided that a slightly modified definition of modular multiplication is adopted. In this paper we propose a novel unified architecture for parallel Montgomery multiplication supporting both GF(N) and GF(2(n)) finite field operations, which are critical for RSA ad ECC public key cryptosystems. the hardware scheme interleaves multiplication and modulo reduction. Furthermore, it relies on a modified Booth recoding scheme for the multiplicand and a radix-4 scheme for the modulus, enabling reduced time delays even for moderately large operand widths. In addition, we present a pipelined architecture based on the parallel blocks previously introduced, enabling very low clock counts and high throughput levels for long operands used in cryptographic applications. Experimental results, based on 0.18 mu m CMOS technology, prove the effectiveness of the proposed techniques, and outperform the best results previously presented in the technical literature.

关键词： Public key cryptography

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parallel applications and on-chip traffic distributions: Observation, implication and modelling

Parallel applications and on-chip traffic distributions: Obs...

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international Joint conference on Software Technologies (ICSOFT)

作者： thomas Canhao Xu Jonne Pohjankukka Paavo Nevalainen Tapio Pahikkala Ville Leppänen Department of Information Technology University of Turku Turku Finland

ISBN: (纸本)9781467385312

We study the traffic characteristics of parallel and high performance computing applications in this paper. Applications that utilize multiple cores are more and more common nowadays due to the emergence of multicore processors. However the design nature of single-threaded applications and multi-threaded applications can vary significantly. Furthermore the on-chip communication profile of multicore systems should be analysed and modelled for characterization and simulation purposes. We investigate several applications running on a full system simulation environment. the on-chip communication traces are gathered and analysed. We study the detailed low-level profiles of these applications. the applications are categorized into different groups according to various parallel programming paradigms. We discover that the trace data follow different parameters of power-law model. the problem is solved by applying least-squares linear regression. We propose a generic synthetic traffic model based on the analysis results.

关键词： Multicore processing Program processors System-on-chip Analytical models Data models Protocols Computational modeling

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the GPU-based String Matching System in Advanced AC Algorithm

The GPU-based String Matching System in Advanced AC Algorith...

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international conference on Computer and Information Technology (CIT)

作者： Jiangfeng Peng Hu Chen Shaohuai Shi School of Computer Science and Engineering South China University of Technology Guangzhou China

As one of the most pervasive problems in computer science, string matching is the kernel algorithm in many applications,which especially within the communities of information retrieval and computational biology. Meanwhile, the CPU+GPU heterogeneous parallel platform becomes more and more popular in solving computing intensive applications. this paper implements the webpage matching system with GPU-based advanced AC algorithm, G-AC, which is almost 28 times peak performance to the original AC algorithm which is referred from Snort.

关键词： Graphics processing unit Instruction sets Automata Pattern matching Algorithm design and analysis Memory management Data structures

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Unified weighted label propagation algorithm using connection factor 12th

Unified weighted label propagation algorithm using connectio...

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12th international conference on Advanced Data Mining and Applications, ADMA 2016

作者： Wang, Xin Jian, Songlei Lu, Kai Wang, Xiaoping College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9783319495859

With the social networks getting increasingly larger, fast community detection algorithms like the label propagation algorithm, are attracting more attention. But the label propagation algorithm deals vertices with no proper weight, which leads to the loss in the performance. We propose the connection factor of the vertex to measure its influence on the local connectivity. the connection factor can reveal the topological structure feature, and we propose a unified weight to modify the original label propagation algorithm. Experiments show that our Unified Weighted LPA has an average performance promotion from 5% to 10 %, in the best case more than 30%. © Springer international Publishing AG 2016.

关键词： Population dynamics

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Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning

Bridging the FPGA programmability-portability Gap via automa...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Konstantinos Krommydas Ruchira Sasanka Wu-chun Feng Dept. of Computer Science Virginia Tech Intel Corporation

ISBN: (纸本)9781509015047

Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.

关键词： Kernel Field programmable gate arrays Optimization parallel processing Programming Visualization Shift registers

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High Performance Implementation of ARIA Encryption Algorithm on Graphics processing Units

High Performance Implementation of ARIA Encryption Algorithm...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Limin Xiao Yongnan Li Li Ruan Guangchao Yao Deguo Li School of Computer Science and Engineering Beihang University Beijing China

It becomes increasingly common to use GPU (Graphics processing Units) as accelerators to speed up compute intensive sections of applications. Since block ciphers are supposed to be used for high speed encryption, it is important to implement them as fast as possible. Block cipher ARIA is a new type of encryption standard with four different S-boxes. this paper proposes three methods of high performance implementations of ARIA encryption algorithm on GPU. In order to reduce the data dependency, the round function of ARIA are merged into lookup tables and XOR operations. Encrypting process is performed in parallel and all the data in different GPU memory spaces are arranged properly. Experimental results demonstrate that these techniques accelerate the speed of ARIA encryption significantly. the quantitative performance comparison demonstrates acceleration up to 18 - 45 times speedup while the size of plaintext varies from 4M to 256M.

关键词： Instruction sets Encryption Graphics processing units Indexes Resource management Ciphers Synchronization

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An incremental benchmark suite for performance tuning of parallel discrete event simulation

An incremental benchmark suite for performance tuning of par...

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Annual Hawaii international conference on System Sciences (HICSS)

作者： R. Ronngren L. Barriga R. Ayani Department of Teleinformatics Royal Institute of Technology Stockholm Sweden

parallel simulation has been an active research area for more than a decade, and several parallel simulation algorithms have been proposed. To evaluate parallel simulation environments, there is a need for a common benchmark suite. Such benchmarks should allow the designer of simulation kernels to: (i) evaluate how efficiently the simulation kernel runs on specific architectures; and (ii) evaluate how simulation problems scale on the kernel. A vast majority of benchmarks suggested in the literature focus on the latter problem. the first requirement is however equally important, as such benchmarks are needed to implement efficient simulation systems. In this report, we advocate an incremental benchmark methodology which is primarily intended for performance tuning. the benchmark suite is based on a small set of ping models with which it is possible to effectively isolate and estimate various overheads, contention and latencies encountered in simulation kernels. the use of the benchmark suite is illustrated by its application to performance tuning and evaluation of a time warp kernel.

关键词： Discrete event simulation Computational modeling Kernel Computer simulation Computer architecture Performance analysis Communication networks parallel processing Delay Application software

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