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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Power-Performance Comparison of Single-Task Driven Many-Cores

Power-Performance Comparison of Single-Task Driven Many-Core...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Fuat Keceli Tali Moreshet Uzi Vishkin Department of Electrical and Computer Engineering University of Maryland USA Department of Engineering Swarthmore College USA

Many-cores, processors with 100s of cores, are becoming increasingly popular in general-purpose computing, yet power is a limiting factor in their performance. In this paper, we compare the power and performance of two design points in the many-core processor domain. the XMT general-purpose processor provides significant runtime advantage on irregular parallel programs (e.g., graph algorithms). this was previously demonstrated and tied to its architecture choices and ease-of-programming. In contrast, current commercial GPUs excel at regular parallel programs that require high processing capability. In this work, we set the power envelope as a constraint and evaluate an envisioned 1024-core XMT processor against an NVIDIA GTX280 GPU considering various scenarios for estimating the power of the XMT chip. Even under worst-case assumptions and scenarios, simulations show that the XMT processor sustains its advantage over the GPU on irregular parallel programs, while not falling significantly behind on regular programs. the total energy spent per benchmark fits a similar pattern. Given that the two architectures target different types of parallelism, a future system can potentially utilize an XMT chip and a GPU chip in complementary roles.

关键词： Benchmark testing Graphics processing unit Computer architecture Temperature measurement Clocks Random access memory

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A heterogeneous parallel accelerator for image analysis and radar signal processing

A heterogeneous parallel accelerator for image analysis and ...

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Annual Hawaii international conference on System Sciences (HICSS)

作者： M. Anderson J.D. Yesberg A.J.S. Yakovleff D.A. Krnak P.C. Drewer C.R. Watson M. Cavaiuolo Defence Science and Technology Organisation Australia

the highly specialised Neural Accelerator Board (NAB), and the Shiva (a reconfigurable multiprocessor) are two architectures designed to augment general purpose workstations. the NAB uses custom VLSI components to perform weighted 10-bit fixed-point multiply/accumulate operations at a total rate of 20 giga-operations per second. the Shiva uses Intel i860 microprocessors to achieve a good balance of floating point, graphics, and integer performance. the two can be combined into a heterogeneous, reconfigurable multiprocessor, which has applications in image analysis and radar signal processing. this paper outlines the benefits of heterogeneity and reconfigurability. A description is given of the architectures of the NAB and the Shiva, with details of the proposed applications.< >

关键词： Image analysis Radar signal processing Computer architecture Signal processing algorithms Australia Workstations Microprocessors Acceleration Reduced instruction set computing Hardware

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parallel Dense Gauss-Seidel Algorithm on Many-Core Processors

Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Hadrien Courtecuisse Jérémie Allard INRIA Lille Nord Europe France

the Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing methods, taking advantage of recent many-cores architectures offering fast synchronization primitives. Experimental results on both multi-core CPUs and recent GPUs show that our proposed method is able to fully exploit the available units, whereas trivial parallel algorithms often fail. this method is illustrated by an application in medical intervention planning, where it is used to solve a linear complementary problem (LCP) expressing the contacts applied to a deformable body.

关键词： Gaussian processes High performance computing parallel processing Concurrent computing Jacobian matrices Computer architecture Equations Pervasive computing Linear systems Europe

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parallel Implementation of Chaos Neural Networks for an Embedded GPU

Parallel Implementation of Chaos Neural Networks for an Embe...

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IEEE international conference on Awareness Science and Technology

作者： Zhongda Liu Takeshi Murakami Satoshi Kawamura Hitoaki Yoshida Faculty of Science and Engineering Ishinomaki Senshu University Ishinomaki Japan Technical Division Iwate University Morioka Japan Faculty of Humanities Morioka University Takizawa Japan Faculty of Education Iwate University Morioka Japan

the Internet of things (IoT) has become ubiquitous, and the need for higher information security is increasing. the CPU usage cost of IoT devices to process information security tasks is large. In the present paper, we study a parallel implementation of chaos neural networks for an embedded GPU using the Open Computing Language (OpenCL). We evaluate this parallel implementation, and the results indicate that it can extract a pseudo-random number series at high speed and with low CPU usage. this implementation is remarkably faster than the implementation in the CPU and is approximately 49% faster than AES in counter mode. the rate of pseudo-random number generation is higher than 2.1 Gbps when using 100 compute units of a GPU. Applying a stream cipher is sufficient even for Internet communication. Extracted pseudo-random number series are independent, have fine randomness properties, and can merge into one series applied to a stream cipher.

关键词： Graphics processing units Time series analysis Ciphers NIST Internet of things Central processing Unit Neurons

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Improving QoS of audio and video packets in MPLS using network processors

Improving QoS of audio and video packets in MPLS using netwo...

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IEEE international conference on Networks

作者： B. Kaarthick N. Nagarajan S. Rajeev R. Joanna Angeline Sri Krishna College of Engineering and Technology Coimbatore India Coimbatore Institute of Engineering and Information Technology Coimbatore India Wipro Technologies Limited Chennai India Tata Consultancy Services Limited Chennai India

Growing bandwidth demand in the Internet requires new algorithms and architectures to provide a high degree of QoS. Further, to complicate the problem of Traffic Engineering, real time data processing requires more priority than non-real time data processing. In this paper, we present an effective solution for improving QoS of audio and video packets in MPLS networks under real time traffic conditions. the contribution of this work is two fold. First, we investigate the impact of increased traffic on QoS parameters under heavy loading conditions and further we propose an efficient routing mechanism based on active networking concepts [1] to satisfy QoS requirements of audio and video packets.

关键词： Multiprotocol label switching Telecommunication traffic Delay Bandwidth Protocols Application specific integrated circuits parallel processing Data processing Communication system traffic control Educational institutions

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Convergence throughput gain in a unified parallel turbo receiver

Convergence throughput gain in a unified parallel turbo rece...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Atif Raza Jafri Amer Baghdadi CESAT Islamabad Pakistan TELECOM Bretagne Brest France

ISBN: (纸本)9781467344258

In pursuit of bringing high end applications on radio platforms, recent and evolving wireless standards impose stringent requirements in the shape of high throughputs, error rate performance close to theoretical limits and multi mode transmissions to efficiently use bandwidth in different channel conditions. In the presence of these requirements, the designer comes across contradicting requirements. In fact, in order to handle error rate performance the iterative (Turbo) processing (Turbo/LDPC decoding, Turbo demodulation and Turbo Equalization) is common implementation practice in baseband receivers. However, this creates bottleneck in achieving imposed throughputs. In this scenario, parallelism study and resulting throughput gains while keeping same error rate convergence, provides the designer concrete results to establish compromise among design constraints. In this paper, first of all three level of parallelism study is presented on turbo decoding, turbo demodulation and MIMO turbo equalization. To aid the designer in taking decision during the design, mathematical expressions for throughput gain in unified parallel turbo receiver are provided. throughput gain for different system scenarios are computed by using system parameters and simulation results in derived expressions.

关键词： Decoding parallel processing Vectors throughput Receivers Equalizers MIMO

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Marıa del Carmen Calatrava Moreno thomas Auzinger Technische Universitat Wien Wien Wien AT Institute of Computer Graphics and Algorithms Vienna University of Technology Vienna Austria

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing units Hardware Computer architecture Graphics Instruction sets Computational modeling Semiconductor optical amplifiers

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Scalable and parallel Implementation of a Financial Application on a GPU: With Focus on Out-of-Core Case

Scalable and Parallel Implementation of a Financial Applicat...

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international conference on Computer and Information Technology (CIT)

作者： Myungho Lee Jin-hong Jeon Joonsuk Kim Joonhyun Song Department of Computer Science and Engineering Myoneji University Yongin si Gyeonggi South Korea

the architecture of the latest Graphic processing Unit (GPU) consists of a number of uniform programmable units integrated on the same chip, which facilitate the general-purpose computing beyond the graphic processing. With the multiple programmable units executing in parallel, the latest GPU shows superior performance for many non-graphic applications. Furthermore, programmers can have a direct control on the GPU pipeline using easy-to-use parallel programming environments. these advances in hardware and software make General-Purpose GPU computing (GPGPU) widespread. In this paper, we parallelize a computationally demanding financial application and optimize its performance on a latest GPU. We also analyze the performance results compared with those obtained using CPU only. Experimental results show that GPU can achieve a superior performance, greater than 190x, compared with the CPU-only case when the data fits in the graphic memory. We also address the performance issue in the out-of-core case where the data cannot fit in the device memory on the GPU. In such a case, by using streaming technique helps make up the performance gap lost due to data transfer overhead from the CPU side to the GPU DRAM.

关键词： Graphics processing unit Monte Carlo methods Instruction sets Computational modeling Kernel Arrays Random variables

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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

VLSI-based parallel architecture for block-matching motion e...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Donglai Xu J. Bentley School of Science and Technology University of Teesside Middlesbrough UK

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

关键词： parallel architectures Motion estimation Video coding Computer architecture Very large scale integration Field programmable gate arrays Circuits Costs Pipelines Silicon

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A massively parallel architecture for linear machine code genetic programming 4th

A massively parallel architecture for linear machine code ge...

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4th international conference on Evolvable Systems: From Biology to Hardware, ICES 2001

作者： Eklund, Sven E. Dalama University Sweden

ISBN: (纸本)354042671X

Over the last decades Genetic algorithms (GA) and Genetic Programming (GP) have proven to be efficient tools for a wide range of applications. However, in order to solve human-competitive problems they require large amounts of computational power, particularly during fitness calculations. In this paper I propose the implementation of a massively parallel model in hardware in order to speed up GP. this fme-grained diffusion architecture has the advantage over the popular Island model of being VLSI-friendly and is therefore small and portable, without sacrificing scalability and effectiveness. the diffusion architecture consists of a large amount of independent processing nodes, connected through an X-net topology, that evolve a large number of small, overlapping sub-populations. Every node has its own embedded CPU, which executes a linear machine code representation of the individuals. Preliminary simulation results (low-level VHDL simulation) indicate a performance of 10.000 generations per second (depending on the application). One node requires 10-20.000 gates including the CPU (also application dependent), which makes it possible to fit up to 2.000 individuals in one FPGA (Virtex XC2V10000). © Springer-Verlag Berlin Heidelberg 2001.

关键词： Genetic programming

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