检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,691 篇 会议
58 册 图书
54 篇 期刊文献

馆藏范围

2,803 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,845 篇 工学
- 1,629 篇 计算机科学与技术...
- 847 篇 软件工程
- 340 篇 电气工程
- 222 篇 电子科学与技术（可...
- 209 篇 信息与通信工程
- 84 篇 控制科学与工程
- 63 篇 光学工程
- 57 篇 机械工程
- 41 篇 仪器科学与技术
- 39 篇 生物医学工程（可授...
- 38 篇 生物工程
- 31 篇 材料科学与工程（可...
- 25 篇 动力工程及工程热...
- 21 篇 化学工程与技术
- 20 篇 建筑学
- 15 篇 土木工程
- 13 篇 力学（可授工学、理...
- 12 篇 交通运输工程
500 篇 理学
- 343 篇 数学
- 113 篇 物理学
- 51 篇 系统科学
- 48 篇 生物学
- 30 篇 统计学（可授理学、...
- 26 篇 化学
173 篇 管理学
- 119 篇 管理科学与工程(可...
- 62 篇 图书情报与档案管...
- 49 篇 工商管理
40 篇 医学
- 30 篇 临床医学
- 14 篇 基础医学(可授医学...
15 篇 法学
- 15 篇 社会学
9 篇 经济学
9 篇 农学
8 篇 文学
2 篇 军事学
1 篇 教育学

主题

360 篇 parallel process...
219 篇 computer archite...
205 篇 graphics process...
146 篇 parallel archite...
135 篇 graphics process...
129 篇 hardware
116 篇 parallel algorit...
112 篇 image processing
98 篇 computational mo...
94 篇 concurrent compu...
87 篇 instruction sets
86 篇 field programmab...
83 篇 algorithm design...
79 篇 multicore proces...
77 篇 signal processin...
76 篇 parallel process...
66 篇 parallel program...
60 篇 gpu
59 篇 throughput
59 篇 kernel

机构

11 篇 natl univ def te...
6 篇 college of compu...
6 篇 school of comput...
6 篇 hosei univ dept ...
6 篇 natl univ def te...
5 篇 univ aizu dept c...
5 篇 carleton univ sc...
5 篇 school of comput...
5 篇 computer science...
5 篇 inria rennes
5 篇 city university ...
4 篇 chinese acad sci...
4 篇 univ michigan ad...
4 篇 institute of com...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 univ jaume 1 dep...
4 篇 hainan internati...
4 篇 tech univ cluj n...
4 篇 department of co...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
9 篇 konrad karczewsk...
9 篇 quintana-orti en...
7 篇 dongarra jack
7 篇 kothapalli kisho...
6 篇 hannig frank
6 篇 liu jie
6 篇 su jinshu
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wyrzykowski roma...
6 篇 thulasiraman par...
5 篇 ito yasuaki
5 篇 jerzy waśniewski
5 篇 wang guojun
5 篇 geyong min
5 篇 wanlei zhou

语言

2,757 篇 英文
21 篇 其他
15 篇 中文
11 篇 俄文
2 篇 乌克兰文
1 篇 西班牙文

检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2803 条记录，以下是241-250 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Handwritten Signature Recognition using parallel CNNs and Transfer Learning for Forensics

Handwritten Signature Recognition using Parallel CNNs and Tr...

引用

international conference on Control, Decision and Information Technologies (CoDIT)

作者： Jaouhar Fattahi Feriel Sghaier Mohamed Mejri Ridha Ghayoula Emil Pricop Baha Eddine Lakdher Department of Computer Science and Software Engineering Laval University Quebec Canada Carthage National Engineering School Carthage University Tunis Tunisia Faculty of Engineering University of Moncton Canada Computers & Electronics Department Automatic Control Petroleum-Gas University of Ploieşti Ploieşti Romania Faculty of Science University of Monastir Monastir Tunisia

ISBN: (数字)9798350373974

ISBN: (纸本)9798350373981

Handwritten signatures hold paramount importance in legal, financial, and administrative domains, necessitating the development of robust signature recognition tools for forensic applications. this paper introduces a handwritten signature recognition (HSR) model employing parallel Convolutional Neural Networks (CNN) tailored for forensic endeavors. Utilizing the parallel processing capabilities of CNN, our proposed approach adeptly analyzes and extracts discriminative features from handwritten signature images to facilitate precise recognition. In addition, we leverage several transfer learning techniques by parallelizing proven pre-trained CNNs. Extensive experimentation validates the efficacy of our approach on a standard dataset, demonstrating high accuracy and resilience in signature recognition tasks. the proposed approach exhibits substantial promise in augmenting forensic investigations by automating signature verification processes, thereby bolstering fraud detection efforts and upholding the integrity of legal documentation.

关键词： Deep learning Handwriting recognition Forensics Face recognition Transfer learning Feature extraction Fraud Convolutional neural networks Standards Resilience

来源：评论

学校读者我要写书评

暂无评论

Proceedings of IA3 2020: 10th Workshop on Irregular Applications: architectures and algorithms, Held in conjunction with SC 2020: the international conference for High Performance Computing, Networking, Storage and Analysis

Proceedings of IA3 2020: 10th Workshop on Irregular Applicat...

引用

10th Workshop on Irregular Applications: architectures and algorithms, IA3 2020

ISBN: (纸本)9780738110905

the proceedings contain 8 papers. the topics discussed include: accelerating domain propagation: an efficient GPU-parallel algorithm over sparse matrices;parallelizing irregular computations for molecular docking;reducing queuing impact in irregular data streaming applications;supporting irregularity in throughput-oriented computing by SIMT-SIMD integration;DistDGL: distributed graph neural network training for billion-scale graphs;labeled triangle indexing for efficiency gains in distributed interactive subgraph search;distributed memory graph coloring algorithms for multiple GPU;and performance evaluation of the vectorizable binary search algorithms on an FPGA platform.

关键词：

来源：评论

学校读者我要写书评

暂无评论

StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs

StencilStream: A SYCL-based Stencil Simulation Framework Tar...

引用

international conference on Field Programmable Logic and Applications

作者： Jan-Oliver Opdenhövel Christoph Alt Christian Plessl Tobias Kenter Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Friedrich Alexander Universität Erlangen

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Although High-Level Synthesis has dramatically improved the usability of FPGAs in High-Performance Computing applications, it still requires much experience to create well-performing FPGA designs. We introduce the stencil simulation framework StencilStream to separate the concerns of performance engineers and domain scientists. We have formulated our performance-oriented stencil simulation designs for FPGAs along with their management code as C++ templates using SYCL language features. Application developers instantiate these templates with their concrete stencil code and obtain a complete application with little management overhead. In this work, we describe the most interesting API features and the two backend architectures of StencilStream, along with their corresponding performance models. We then evaluate the performance of the architectures using three manually implemented sample applications and highlight the real-world usability of StencilStream further with shallow water simulations obtained from a code-generation flow. Compiled with Intel oneAPI for an Intel Stratix 10 GX 2800 target FPGA, the best-performing sample design exceeds a throughput of 1 TFLOPS.

关键词： Productivity Codes High performance computing Graphics processing units Computer architecture throughput Logic Usability Field programmable gate arrays Engines

来源：评论

学校读者我要写书评

暂无评论

Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs 21

Multiple Transform Selection concept modeling and implementa...

引用

14th Workshop on Design and architectures for Signal and Image processing, DASIP 2021, held jointly with the 16th HiPEAC conference

作者： Haggui, Naouel Belghith, Fatma Hamidouche, Wassim Masmoudi, Nouri Nezan, Jean-François Ietr Laboratory Insa Rennes France National School of Engineering of Sfax Tunisia

ISBN: (纸本)9781450389013

Recent studies predict that video data accounts for 82% of Internet traffic by 2022. this fact has motivated MPEG to define a new Video Coding Standard called Versatile Video Coding (VVC), which will be released by the end of 2020. VVC will offer the possibility to handle new video formats and to improve significantly video compression over its predecessor HEVC. Indeed, the objective is to reduce the necessary bit rate by half, at equivalent quality. these advances require the use of more complex algorithms, although the increase in complexity has been limited throughout the standardization process. In order to decrease the complexity of VVC and consequently the coding execution time, several methods have been introduced at different stages of the encoder. the aim of this paper is to explore the available parallelism of VVC to accelerate the coding and the decoding processes. this paper focuses on the transformation block and more specifically the new concept of Multiple Transform Selection (MTS) introduced by VVC. Moreover, a study of several granularity levels of Interface-Based Synchronous Dataflow (IBSDF) models and their impact on the performances obtained on x86 architectures is presented. IBSDF dataflow graph has been developed to reveal the available parallelism of MTS. the PREESM fast prototyping tool is then used for the mapping and the scheduling of MTS on virtual and real parallel architectures and for generating efficient parallel implementations on real architectures. PREESM has been used in this work to explore the potential parallelism offered by MTS and to prove the efficiency of MTS on multicore x86 architectures. Experimental results show a speed-up close to the optimum. © 2021 ACM.

关键词： Video signal processing

来源：评论

学校读者我要写书评

暂无评论

parallel Quantum Computation Approach for Quantum Deep Learning and Classical-Quantum Models 10

Parallel Quantum Computation Approach for Quantum Deep Learn...

引用

10th international conference on Mathematical Modeling in Physical Sciences, IC-MSQUARE 2021

作者： Payares, E.D. Martinez-Santos, J.C. Faculty of Engineering Universidad Tecnológica de Bolívar Cartagena de Indias Colombia

the paradigm of Quantum computing and artificial intelligence has been growing steadily in recent years and given the potential of this technology by recognizing the computer as a physical system that can take advantage of quantum mechanics for solving problems faster, more efficiently, and accurately. We suggest experimentation of this potential through an architecture of different quantum models computed in parallel. In this work, we present encouraging results of how it is possible to use Quantum processing Units analogically to Graphics processing Units to accelerate algorithms and improve the performance of machine learning models through three experiments. the first experiment was a reproduction of a parity function, allowing us to see how the convergence of a given Quantum model is influenced significantly by computing it in parallel. For the second and third experiments, we implemented an image classification problem by training quantum neural networks and using pre-trained models to compare their performances with the same experiments carried out with parallel quantum computations. We obtained very similar results in the accuracies, which were close to 100% and significantly improved the execution time, approximately 15 times faster in the best-case scenario. We also propose an alternative as a proof of concept to address emotion recognition problems using optimization algorithms and how execution times can be positively affected by parallel quantum computation. To do this, we use tools such as the cross-platform software library PennyLane and Amazon Web Services to access high-end simulators with Amazon Braket and IBM quantum experience. © 2021 Institute of Physics Publishing. All rights reserved.

关键词： Quantum theory

来源：评论

学校读者我要写书评

暂无评论

A C++ Library for Memory Layout and Performance Portability of Scientific Applications 28th

A C++ Library for Memory Layout and Performance Portabilit...

引用

28th international European conference on parallel and Distributed Computing , Euro-Par 2022

作者： Incardona, Pietro Gupta, Aryaman Yaskovets, Serhii Sbalzarini, Ivo F. Technische Universität Dresden Faculty of Computer Science Dresden Germany Max Planck Institute of Molecular Cell Biology and Genetics Dresden Germany Center for Systems Biology Dresden Dresden01307 Germany Center for Scalable Data Analytics and Artificial Intelligence ScaDS.AI Dresden/Leipzig Germany

ISBN: (纸本)9783031312083

We present a C++14 library for performance portability of scientific computing codes across CPU and GPU architectures. Our library combines generic data structures like vectors, multi-dimensional arrays, maps, graphs, and sparse grids with basic, reusable algorithms like convolutions, sorting, prefix sum, reductions, and scan. the memory layout of the data structures is adapted at compile-time using tuples with optional memory mirroring between CPU and GPU. We combine this transparent memory mapping with generic algorithms under two alternative programming interfaces: a CUDA-like kernel interface for multi-core CPUs, Nvidia GPUs, and AMD GPUs, as well as a lambda interface. We validate and benchmark the presented library using micro-benchmarks, showing that the abstractions introduce negligible performance overhead, and we compare performance against the current state of the art. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays

Analysis and Optimization of Block LU Decomposition for Exec...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Dominik Walter thomas Adamtschuk Frank Hannig Jürgen Teich Department of Computer Science Hardware/Software Co-Design Friedrich-Alexander-Universitat Erlangen-Niirnberg (FAU) Germany

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

LU decomposition is a widely used application for solving systems of linear equations. It involves decomposing a given matrix into a lower and upper triangular matrix. But if the matrix size is large, using a block-based LU decomposition on smaller submatrices can be advantageous. this approach allows for an adaptation to a target architecture's memory and computing resources. In this paper, we analyze different strategies for mapping block LU decompositions onto Tightly Coupled Processor Arrays (TCPAs). Each decomposition introduces a dependence graph of matrix operations of smaller size: an unblocked LU decomposition, a triangular matrix solver, and a general matrix-matrix multiplication. First, we propose one piecewise regular algorithm for each corresponding loop nest, analyze its complexity, and then explore various reuse schemes for configuration, data, and synchronization. It will be shown that these schemes have a significant impact on the execution time of the entire algorithm and must be considered by the scheduling approach that governs the individual loop program invocations. Our performance analysis of the mapped block LU decomposition shows a maximal speedup of 12 on a TCPA of size $4\times 4$ compared to a CPU, and a measured speedup of 10 measured on an FPGA-based SoC.

关键词： Schedules Runtime Systems architecture Transforms parallel processing Size measurement Complexity theory

来源：评论

学校读者我要写书评

暂无评论

TPC-NAS: Simple and Effective Neural Architecture Search Based on Total Path Count

TPC-NAS: Simple and Effective Neural Architecture Search Bas...

引用

IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ming-Shan Huang Pi-Chuan Chen Tzi-Dar Chiueh National Taiwan University Taipei Taiwan

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

With the explosive growth of neural network (NN) research and application areas, there is a pressing need to automate the NN model search process in order to attain optimal performance. Nevertheless, existing neural architecture search (NAS) algorithms are time-consuming, resource-intensive, and predominantly tailored for image-related applications. this paper presents the Total Path Count (TPC) score, a straightforward yet highly efficient accuracy predictor solely reliant on the architectural information of a model. the effectiveness of the TPC score is underscored by a robust rank correlation of 0.96 between TPC scores and the accuracies of CIFAR100 architectures. We further introduce TPC-NAS, a zero-shot NAS method that can complete a NAS task in under five CPU minutes without training and inference. TPC-NAS has found wide-ranging applications and it outperforms many other NAS solutions. In image classification, TPC-NAS achieves 78.3% ImageNet top-1 accuracy with 399M FLOPs, while in object detection, it improves mAP by at least 2% over other NAS-derived models. Moreover, TPC-NAS successfully discovers a super-resolution architecture with < 300K parameters and achieves 32.09dB PSNR. In NLP, TPC-NAS delivers a model that matches tinyBERT’s FLOPs but outperforms it by almost 10% in accuracy. these experiments illustrate TPC-NAS’s ability to rapidly generate high-performance CNN/transformer architectures for various applications.

关键词： Training Accuracy Superresolution Object detection Artificial neural networks Natural language processing Central processing Unit

来源：评论

学校读者我要写书评

暂无评论

Improved GAI-BP Detection for MIMO Systems Based on Message Post-processing

Improved GAI-BP Detection for MIMO Systems Based on Message ...

引用

international conference on ASIC

作者： Ruiyang Ji Wenyue Zhou Xiaosi Tan Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-Communication and Signal-Processing (LEADS) National Mobile Communications Research Laboratory Southeast University Nanjing China Purple Mountain Laboratories Nanjing China

Multiple-input multiple-output serves as a key technique for modern wireless communication systems but brings big challenges in data detection. Belief propagation (BP) detection enjoys advances for its near-optimal error rate performance and strong robustness. However, the state-of-art BP detection algorithms suffer from either an exponentially increasing computational complexity or sub-optimal error rate performance. To address this issue, this paper proposes an efficient variant based on the real-domain GAI BP (RD-GAI-BP), called the improved RD-GAI-BP, achieving a better error rate performance at the expense of acceptable complexity increments. Numerical results demonstrate that, in the MIMO scenario with N r = 16, N t = 8 and 64-QAM modulation, the proposed improved RD-GAI-BP earns more than 2 dB SNR gains at the BER of 10 -3 when compared with the state-of-art RD-GAI-BP detection.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Scalable parallel Static Learning 5

Scalable Parallel Static Learning

引用

5th IEEE international Test conference in Asia (ITC-Asia)

作者： Lin, Xiaoze Lai, Liyang Li, Huawei Shantou Univ Guangdong Prov Key Lab Digital Signal & Image Pro Elect Engn Shantou Guangdong Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

ISBN: (纸本)9781665413343

Static learning is a learning algorithm for finding additional implicit implications between gates in a netlist. In automatic test pattern generation (ATPG) the learned implications help recognize conflicts and redundancies early, and thus greatly improve the performance of ATPG. though ATPG can further benefit from multiple runs of incremental or dynamic learning, it is only feasible when the learning process is fast enough. In the paper, we study speeding up static learning through parallelization on heterogeneous computing platform, which includes multi-core microprocessors (CPUs), and graphics processing units (GPUs). We discuss the advantages and limitations in each of these architectures. With their specific features in mind, we propose two different parallelization strategies that are tailored to multi-core CPUs and GPUs. Speedup and performance scalability of the two proposed parallel algorithms are analyzed. As far as we know, this is the first time that parallel static learning is studied in the literature.

关键词： static learning parallel acceleration GPU multicore CPU

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共281页 << < 21 22 23 24 25 26 27 28 29 30 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：