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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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A parallel Low Latency Bus on Chip for Packet processing MPSoC

A Parallel Low Latency Bus on Chip for Packet Processing MPS...

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2010 10th IEEE international conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Ai-Nv An Pei-Yan Liu Yan-Long Wang Kang Li You-Yang Zou Pei-Jun Ma Yue Hao School of microelectronics of Xidian University Xi'an 710071 China School of microelectronics of Xidian niversity Xi'an 710071 China

In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. the high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed architecture is improved up to 2.3 times than the one of the AHB buses and reduce communication latency about 45％ than the later. Moreover, the bus arbiter implementation has reasonable area and timing cost which make it suitable for high performance IP-packet or base-band processing.

关键词： throughput SDRAM Topology Bandwidth Computer architecture Data buses

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A Tool for Real-Time Performance Monitoring of parallel and Distributed Systems

A Tool for Real-Time Performance Monitoring of Parallel and ...

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IEEE Region 10 international conference TENCON

作者： D. Bhatt T. Steeves D. Lee Honeywell Systems and Research Center Inc. Minneapolis MN USA

this paper presents the concepts, architecture, and features of a tool for instrumenting parallel and distributed systems. this capability will be useful in evaluating alternative architectures and strategies for distributing application software, detecting performance bottlenecks, quantifying and fine-tuning real-time performance, detecting and isolating behavior anomalies, and characterizing the behavior of specific algorithms under desired stimulation conditions. the Honeywell instrumentation system provides a flexible capability for selecting and customizing existing instrumentation functions, synthesizing new instrumentation functions, and tailoring/scaling instrumentation to a particular architecture or application domain.

关键词： Real time systems Monitoring Instruments Computer architecture Application software Hardware Performance analysis Debugging Distributed processing Algorithm design and analysis

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Measurement and Control of Linux Operating System Noise on the Godson-3A Shared-Memory Multicore Platform

Measurement and Control of Linux Operating System Noise on t...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Lei Wang Yulong Zhao Zhen Wang School of Computer Science and Engineering Beihang University Beijing China

Operating system (OS) noise refers to the interference experienced by an application due to activities inside an operating system. OS noise can significantly hurt the performance of applications, especially parallel applications. We implemented a tool, noise test, to study the characteristics of OS noise on the Godson-3A shared-memory multicore platform running Linux. We found that OS noise was balanced among cores under uniform memory access (UMA) but not under non-uniform memory access (NUMA). We then implemented another tool, quietcpu, to control OS noise. Tests showed the tool could be used to effectively reduce the maximum noise durations by around 50% and the average noise duration by around 5% on our experiment platform.

关键词： Noise Multicore processing Kernel Linux Noise measurement Synchronization

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Quarter-Rate Implementation of an 1 GSPS 128 Tap FIR Structure used as Cross-correlator in UWB Communication

Quarter-Rate Implementation of an 1 GSPS 128 Tap FIR Structu...

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international conference on Industrial and Information Systems, ICIIS

作者： Tuhin Subhra Chakraborty Saswat Chakrabarti G.S.Sanyal School of Telecommunications Indian Institute of Technology Kharagpur India

Finite impulse response (FIR) filters are widely used in many applications involving signal processing algorithms. the FIR can also be used as a convolver or as a cross-correlator due to its structural similarity. In general the problem with the hardware implementation of FIR is mainly the area complexity and this is much prominent if the number of taps is pretty large. For high throughput application, like UWB communication, the designer is forced to go for parallel-pipelined design and this increases the complexity many fold. parallel architecture is required not only to meet the stringent throughput requirement but also to save power consumption. However an L level parallelization typically increases the number of computations (multiplications + additions) by L times compared to a single level FIR architecture. this increases the area complexity around L times. Typically the area complexity of multiplier is much more than an adder. A significant amount of research work has been conducted to reduce the multiplication complexity of FIR architecture. In this paper we present an adder-tree based multiplier block parallel FIR architecture which reduces the multiplication complexity in many fold compared to standard multiplier based or Canonic Signed Digit (CSD) based multiplier architecture. We also present a simple way of forming the exhaustive adder-tree multiplier block.

关键词： Finite impulse response filter Ultra wideband communication throughput Computer architecture Signal processing algorithms Convolvers Hardware parallel architectures Energy consumption Concurrent computing

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the SABER system for window-based hybrid stream processing with GPGPUs: demo 16

The SABER system for window-based hybrid stream processing w...

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Proceedings of the 10th ACM international conference on Distributed and Event-based Systems

作者： Alexandros Koliousis Matthias Weidlich Raul Castro Fernandez Alexander L. Wolf Paolo Costa Peter Pietzuch Imperial College London Imperial College London and Humboldt-Universität zu Berlin Microsoft Research

ISBN: (纸本)9781450340212

Heterogeneous architectures that combine multi-core CPUs with many-core GPGPUs have the potential to improve the performance of data-intensive stream processing applications. Yet, a stream processing engine must execute streaming SQL queries with sufficient data-parallelism to fully utilise the available heterogeneous processors, and decide how to use each processor in the most effective way. Addressing these challenges, we demonstrate Saber, a hybrid high-performance relational stream processing engine for CPUs and GPGPUs. Saber executes window-based streaming SQL queries in a data-parallel fashion and employs an adaptive scheduling strategy to balance the load on the different types of processors. To hide data movement costs, Saber pipelines the transfer of stream data between CPU and GPGPU memory. In this paper, we review the design principles of Saber in terms of its hybrid stream processing model and its architecture for query execution. We also present a web front-end that monitors processing throughput.

关键词： GPGPUs heterogeneous hardware stream processing

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A novel search engine-based method for discovering command and control server 15th

A novel search engine-based method for discovering command a...

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Guo, Xiaojun Cheng, Guang Pan, Wubin Dinhtu, Truong Liang, Yixin School of Computer Science and Engineering Southeast University Nanjing211189 China Key Laboratory of Computer Network and Information Integration Southeast University Nanjing211189 China School of Information Engineering Xizang Minzu University Xianyang712082 China XiZang Key Laboratory of Optical Information Processing and Visualization Technology Xizang Minzu University Xianyang712082 China

ISBN: (纸本)9783319271361

To solve the problem of getting command and control (C&C) server address covertly for malware of Botnet or advanced persistent threats, we propose a novel C&C-server address discovery scheme via search engine. this scheme is com-posed of five modules. the botmaster uses publish module to issue C&C-server IPs in diaries of several free blogs on Internet firstly. then these diaries could be indexed by search engine (SE). When the infected terminal becomes a bot, it uses keyword production module to produce search keyword and submits some or all these keywords to SEs to obtain the search engine result pages (SERPs). For items in SERPs, the bot uses filtering algorithm to remove noise items and leave valid items whose abstract contain C&C-server IPs. Lastly the bot utilizes extraction and conversion module to extract these C&C-server IPs and translates them into binary format. the experimental results show that our proposed scheme is fully able to discover and obtain C&C-server IPs via various search engines. Furthermore, if we set proper threshold value for SE, it can extract C&C-server IPs accurately and efficiently. © Springer international Publishing Switzerland 2015.

关键词： Search engines

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A hybrid genetic algorithm for privacy and cost aware scheduling of data intensive workflow in cloud 1

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： Chen, Congyang Liu, Jianxun Wen, Yiping Chen, Jinjun Zhou, Dong Key Laboratory of Knowledge Processing and Networked Manufacture Hunan University of Science and Technology Xiangtan411100 China College of Computer Science and Engineering Hunan University of Science and Technology Xiangtan411100 China University of Technology Sydney UltimoNSW2070 Australia

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

In the context of cloud computing and big data, the data of all walks of life has been obtained conveniently. Some information of users in the business process is in need of protection with the popularity of workflow applications, which will greatly affect the scheduling of workflow. Meanwhile, the amount of data is usually very large in workflow, the data privacy protection in workflow has also become an important research problem. In this paper, in order to satisfy the requirement of data privacy protection from user and minimize the total scheduling cost in workflow scheduling, we proposed a privacy and cost aware method based on genetic algorithm for data intensive workflow applications which takes into account computation cost, data transmission cost and data storage cost in cloud to solve this problem on finding the best scheduling solution. the proposed algorithm uses the summation of upward and downward rank values for prioritizing workflow tasks, then merges it to make an optimal initial population to obtain a good solution quickly. Besides, a series of operations like selection, crossover and mutation have been used to optimize the scheduling. In the workflow task scheduling, we assign the datacenter for tasks needing privacy protection, which data of these tasks cannot be moved or copied to other datacenter. Finally, we demonstrate the potential of proposed algorithm for optimizing economic cost with user privacy protection requirement. the experimental results show that proposed algorithm can help improve the scheduling and save the time and cost by an average of 3. 6% and 15. 6% respectively. © Springer international Publishing Switzerland 2015.

关键词： Scheduling

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Declustering techniques for parallelizing temporal access structures

Declustering techniques for parallelizing temporal access st...

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international conference on Data Engineering

作者： V. Kouramajian R. Elmasri A. Chaudhry Office of the Vice President for Research & Information Technology Rice University Houston USA Computer Science Engineering Department University of Texas Arlington Arlington USA

this paper addresses the issues of declustering temporal index and access structures for a single processor multiple independent disk architecture. the temporal index is the Monotonic B/sup +/-Tree which uses the time index temporal access structure. We devise a new algorithm, called multi-level round robin, for assigning tree nodes to multiple disks. the multi-level round robin declustering technique takes advantage of the append-only nature of temporal databases to achieve uniform load distribution, decrease response time, and increase the fanout of the tree by eliminating the need to store disk numbers within the tree nodes. We propose two declustering techniques for the time index access structures; one considers only time proximity while declustering, whereas the other considers both time proximity and data size. We investigate their performance over different types of temporal queries and show that various temporal queries have conflicting allocation criteria for the time index buckets. In addition, we devise two disk partition techniques for the time index buckets. the mutually exclusive technique partitions the disks into disjoint groups, whereas the shared disk technique allows the different types of buckets to share all disks.< >

关键词： Round robin Databases Delay parallel processing Information technology Architecture Utility programs Partitioning algorithms Analytical models Performance analysis

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P2G: A Framework for Distributed Real-Time processing of Multimedia Data

P2G: A Framework for Distributed Real-Time Processing of Mul...

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international conference on parallel processing Workshops (ICPPW)

作者： Havard Espeland Paul B. Beskow Hakon K. Stensland Preben N. Olsen Stale Kristoffersen Carsten Griwodz Pal Halvorsen Department of Informatics Norway Simula Research Laboratory University of Oslo Norway

the computational demands of multimedia data processing are steadily increasing as consumers call for progressively more complex and intelligent multimedia services. New multi-core hardware architectures provide the required resources, but writing parallel, distributed applications remains a labor-intensive task compared to their sequential counter-part. For this reason, Google and Microsoft implemented their respective processing frameworks MapReduce and Dryad, as they allow the developer to think sequentially, yet benefit from parallel and distributed execution. An inherent limitation in the design of these batch processing frameworks is their inability to express arbitrarily complex workloads. the dependency graphs of the frameworks are often limited to directed acyclic graphs, or even pre-determined stages. this is particularly problematic for video encoding and other algorithms that depend on iterative execution. With the Nornir runtime system for parallel programs, which is a Kahn Process Network implementation, we addressed and solved several of these limitations. However, it is more difficult to use than other frameworks due to its complex programming model. In this paper, we build on the knowledge gained from Nornir and present a new framework, called P2G, designed specifically for developing and processing distributed real-time multimedia data. P2G supports arbitrarily complex dependency graphs with cycles, branches and deadlines, and provides both data- and task-parallelism. the framework is implemented to scale transparently with available (heterogeneous) resources, a concept familiar from the cloud computing paradigm. We have implemented an (interchangeable) P2G kernel language to ease development. In this paper, we present a proof of concept implementation of a P2G execution node and some experimental examples using complex workloads like Motion JPEG and K-means clustering. the results show that the P2G system is a feasible approach to multimedia proce

关键词： Kernel Multimedia communication parallel processing Runtime Streaming media Batch production systems Pipelines

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A GPU-enabled solver for time-constrained linear sum assignment problems

A GPU-enabled solver for time-constrained linear sum assignm...

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the international conference on Informatics and Systems (INFOS)

作者： Roberto Roverso Amgad Naiem Mohammed El-Beltagy Sameh El-Ansary Seif Haridi KTH Royal Institute of Technology Sweden Cairo University Egypt Nile University Egypt

ISBN: (纸本)9781424458288;9789774033964

this paper deals with solving large instances of the Linear Sum Assignment Problems (LSAPs) under realtime constraints, using Graphical processing Units (GPUs). the motivating scenario is an industrial application for P2P live streaming that is moderated by a central tracker that is periodically solving LSAP instances to optimize the connectivity of thousands of peers. However, our findings are generic enough to be applied in other contexts. Our main contribution is a parallel version of a heuristic algorithm called Deep Greedy Switching (DGS) on GPUs using the CUDA programming language. DGS sacrifices absolute optimality in favor of a substantial speedup in comparison to classical LSAP solvers like the Hungarian and auctioning methods. We show the modifications needed to parallelize the DGS algorithm and the performance gains of our approach compared to a sequential CPU-based implementation of DGS and a mixed CPU/GPU-based implementation of it.

关键词： Computer languages Peer to peer computing parallel architectures Best practices Application software Paper technology Heuristic algorithms Performance gain Central processing Unit Large-scale systems

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