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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Determining the Factors Affecting the Accuracy of Effort Estimates for Different Application and Task Types

Determining the Factors Affecting the Accuracy of Effort Est...

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Frontiers of Information Technology (FIT)

作者： Saqib Bukhari Ali Afzal Malik Faculty of Information Technology University of Central Punjab Lahore Pakistan

An important asset in the skill set of any software project manager is the ability to somewhat accurately estimate the effort required to develop a software application. Acquiring this asset, however, requires a thorough understanding of the factors that may affect the accuracy of these estimates. this paper presents the results of an empirical study conducted to determine the causes of variation in the accuracy of effort estimations for different application and task types. A Pakistani software house that specializes in developing financial transaction processing applications is chosen for this empirical study. Actual and estimated values for software development effort are gathered and analyzed for four different types of applications - web-based, database, parallel processing, and telephony - each having six different types of tasks i.e. business-development, new features, usability, security, support, and performance. Over 1000 data points are considered. Analysis of the results reveals, for instance, that the effort for web-based applications is mostly underestimated while the effort for telephony applications is mostly overestimated. the underestimation in web-based applications is usually due to a failure to account for the learning curve associated with rapidly changing web technologies while the overestimation in telephony applications is usually due to a failure to account for the usage of third-party components.

关键词： Estimation Software Accuracy Telephony Business Databases parallel processing

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A VLSI architecture for difference picture-based dynamic scene analysis

A VLSI architecture for difference picture-based dynamic sce...

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international conference on Pattern Recognition

作者： N. Ranganathan R. Mehrotra Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa FL USA

An efficient parallel architecture that exploits the parallelism and pipelining possible in the difference picture-based technique (IEEE Trans. on Pattern Analysis and Machi Intelligence, vol. PAMI-3, no.5, p.489-543, (1981); Computer, p.12-18, Aug. (1981)) is presented for dynamic scene analysis. Each processor is organized as a pipeline, and the processor architecture is simple enough that the motion detection and classification system can be implemented on a single VLSI chip. the proposed VLSI architecture and the design of the various components of the basic processor are described. VLSI chip implementation issues are discussed.< >

关键词： Very large scale integration Image analysis Layout Computer architecture Motion analysis Pipeline processing Noise reduction Buffer storage Microelectronics Computer science

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SQL-on-Hadoop: Full circle back to shared-nothing database architectures 40th

SQL-on-Hadoop: Full circle back to shared-nothing database a...

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Proceedings of the 40th international conference on Very Large Data Bases, VLDB 2014

作者： Floratou, Avrilia Minhas, Umar Farooq Özcan, Fatma IBM Almaden Research Center United States

SQL query processing for analytics over Hadoop data has recently gained significant traction. Among many systems providing some SQL support over Hadoop, Hive is the first native Hadoop system that uses an underlying framework such as MapReduce or Tez to process SQL-like statements. Impala, on the other hand, represents the new emerging class of SQL-on-Hadoop systems that exploit a shared-nothing parallel database architecture over Hadoop. Both systems optimize their data ingestion via columnar storage, and promote different file formats: ORC and Parquet. In this paper, we compare the performance of these two systems by conducting a set of cluster experiments using a TPC-H like benchmark and two TPC-DS inspired workloads. We also closely study the I/O efficiency of their columnar formats using a set of micro-benchmarks. Our results show that Impala is 3.3X to 4.4X faster than Hive on MapReduce and 2.1X to 2.8X than Hive on Tez for the overall TPC-H experiments. Impala is also 8.2X to 10X faster than Hive on MapReduce and about 4.3X faster than Hive on Tez for the TPC-DS inspired experiments. through detailed analysis of experimental results, we identify the reasons for this performance gap and examine the strengths and limitations of each system. © 2014 VLDB Endowment.

关键词： MapReduce

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Applying timed-arc Petri nets to improve the performance of the MPEG-2 encoding algorithm

Applying timed-arc Petri nets to improve the performance of ...

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international conference on Multimedia Modeling (MMM)

作者： F.L. Pelayo F. Cuartero V. Valero H. Macia M.L. Pelayo Escuela Politécnica Superior de Albacete University of Castilla La Mancha Albacete Spain

We use a timed extension of Petri nets, the so called timed-arc Petri Nets, for the specification and analysis of the MPEG-2 video encoder. We have computed bounds for the necessary time to encode each type of frame, also we present an improvement on the encoding process which takes advantage of the potential parallelism degree of the MPEG-2 video encoding algorithm, so reaching a 90% of reduction on the time requirements, with respect to the original MPEG-2 encoder.

关键词： Petri nets Encoding Timing Concurrent computing Performance analysis Algebra Fires parallel processing Software design Computer languages

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Experimental Results of a Raspberry Pi Based WMN Testbed for Multiple Flows and Distributed Concurrent processing

Experimental Results of a Raspberry Pi Based WMN Testbed for...

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international conference on Broadband, Wireless Computing, Communication and Applications (BWCCA)

作者： Tetsuya Oda Donald Elmazi Taro Ishitaki Admir Barolli Keita Matsuo Leonard Barolli Graduate School of Engineering Fukuoka Institute of Technology (FIT) Higashi-Ku Fukuoka Japan Rr. “Dritan Hoxha” Logos University Tirana Albania Fukuoka Prefectural Fukuoka Technical High School Sawara-Ku Fukuoka Japan Department of Information and Communication Engineering Fukuoka Institute of Technology (FIT) Higashi-Ku Fukuoka Japan

ISBN: (纸本)9781467383165

Wireless Mesh Networks (WMNs) are attracting a lot of attention from wireless network researchers, because of their potential use in several fields such as collaborative computing and communications. Considering mobility of the terminals, routing is a key process for operation of WMNs. In this paper, we present the implementation of a testbed for WMNs. We analyze the performance of Optimized Link State Routing (OLSR) protocol and parallel distributed processing in an indoor scenario. For evaluation we considered hop count, delay, jitter and processing time metrics. the experimental results show that the nodes in the testbed were communicating smoothly. the processing time for node 1 is smaller than other nodes.

关键词： Ad hoc networks Routing Wireless sensor networks Wireless communication Delays Network topology

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Hardware Multi-processor Design for Highly-Demanding Applications

Hardware Multi-processor Design for Highly-Demanding Applica...

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international conference on Information Technology: New Generations (ITNG)

作者： Lech Jówiak Yahya Jan Technische Universiteit Eindhoven Eindhoven Noord-Brabant NL Eindhoven University of Technology Eindhoven The Netherlands

ISBN: (纸本)9781467359603

this paper focuses on mastering the architecture development of hardware multi-processors for modern highly demanding applications. It presents the results of our analysis of the main issues to be addressed when designing multi-processors for such applications, and discusses our new multi-processor design method which developed to address these issues. We implemented the method in the form of an automatic design exploration tool. Using this tool we performed a large set of design experiments. the experiments demonstrated that without adequately addressing of the discussed design issues it is virtually impossible to construct high-quality hardware multi-processors, and that our design method adequately addresses them.

关键词： Computer architecture parallel processing Parity check codes Program processors Hardware throughput IEEE 802.15 Standards

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Building High-Performance Application Protocol Parsers on Multi-core architectures

Building High-Performance Application Protocol Parsers on Mu...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Kai Zhang Junchang Wang Bei Hua Xinan Tang School of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

Parsing packet payloads according to the syntax and semantics of an application protocol is a key step in analyzing network traffic. However, it is still a challenge to fulfill this task with high speed(10Gbps+) because parsing packets through deep-content analysis to build a corresponding syntax tree requires tremendous computing resources. Multi-core architectures provide a viable solution for building high-performance parsers for application protocols. Existing sequential application protocol parsers are hard to be reused, and building a new protocol parser from scratch is error-prone and time-consuming. this paper proposes a general and efficient approach to building high-performance parallel application protocol parsers on multi-core platforms. First, the open-source lexical analyzer FLEX is used to describe a protocol and generate a sequential parser. then a source-to-source translation is performed to transform the sequential parser into a parallel one. Finally, an efficient parallel run-time system is built by employing lock-free design principles from top to bottom to support multi-threaded execution on multi-core processors. Experimental results show that our parsers achieve nearly 20Gbps for average HTTP packets and 5Gbps for the challenging smaller FIX packets.

关键词： Protocols Pipelines Flexible printed circuits Multicore processing Buildings Servers

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Dynamically reconfigurable FPGA for robotics control

Dynamically reconfigurable FPGA for robotics control

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international conference on Control, Automation, Robotics and Vision (ICARCV)

作者： S. S. Erdogan Ted Shaneyfelt Geok See Ng Abdul Wahab Department of Computer Science University of Hawai Hilo USA Department of Electrical and Computer Engineering University of Technology San Antonio USA School of Computer Engineering Nanyang Technological University Singapore

this paper describes the programming of a reconfigurable environment to handle inverse dynamics computation for robotics control. Instruction parallelism/pipelining and avoidance of carry propagation while evaluating a lengthy sequence of sum of products is proposed. the difficulties of programming a reconfigurable platform are overcome by defining a fixed processing Element (PE) model with multiple processing components and using microinstructions to drive the PEs. the resulting hardware could be static but could be reconfigured on the fly to provide fault tolerance characteristics. Major considerations while mapping various elements of the design to the FPGA includes the size of the area to be mapped and communication issues related to their communication. Area size selection is compared to the page size selection in operating system design. Communication issues between modules are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files is discussed.

关键词： Field programmable gate arrays Robot control Dynamic programming Robot programming parallel processing Pipeline processing Hardware Fault tolerance Operating systems Software engineering

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Approximate Sorting Check Node processing in Non-Binary LDPC Decoders

Approximate Sorting Check Node Processing in Non-Binary LDPC...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Dimitris Chytas Vassilis Paliouras University of Patras Patras Greece

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

this paper proposes the use of parallel approximate sorting networks in Non-Binary LDPC decoders and quantifies their impact in terms of performance and complexity. Motivated by the messages truncation concept of the Extended Min Sum (EMS) algorithm and the reduction it induces on the decoding complexity, we seek for an approximate parallel sorting strategy for the Elementary Check Node (ECN) Unit processing in the EMS algorithm. We quantify the impact of parallel approximate sorting on both error correction decoding performance and hardware complexity. Bubble check sorting methods are compared to proposed parallel approximate sorting techniques in terms of BER vs. noise plots. Furthermore hardware synthesis results are provided to demonstrate the effects of parallel sorting networks on area and throughput. In certain cases of practical interest, a modest degradation of 0.2 dB in coding gain is imposed; however due to proposed parallel approximate sorters, the latency of ECN can be reduced by up to a factor of two or be logarithmic to the input sequence length, in certain architectures. To better illustrate the impact of the proposed techniques, a complete NB-LDPC decoder has been implemented and used for evaluation; it is found that a substantial reduction in the number of clock cycles required per decoding iteration is achieved by the proposed techniques, more than 50% in certain cases.

关键词： Sorting Decoding Complexity theory Parity check codes Approximation algorithms Degradation Signal to noise ratio

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High-speed elliptic curve cryptography on the NVIDIA GT200 graphics processing unit

High-speed elliptic curve cryptography on the NVIDIA GT200 g...

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10th international conference on Information Security Practice and Experience, ISPEC 2014

作者： Cui, Shujie Großschädl, Johann Liu, Zhe Xu, Qiuliang Shandong University School of Computer Science and Technology Shunhua Road 1500 Jinan 250101 Shandong China University of Luxembourg Laboratory of Algorithmics Cryptology and Security 6 rue Richard Coudenhove-Kalergi L-1359 Luxembourg Luxembourg

ISBN: (纸本)9783319063195

this paper describes a high-speed software implementation of Elliptic Curve Cryptography (ECC) for GeForce GTX graphics cards equipped with an NVIDIA GT200 Graphics processing Unit (GPU). In order to maximize throughput, our ECC software allocates just a single thread per scalar multiplication and aims to launch as many threads in parallel as possible. We adopt elliptic curves in Montgomery as well as twisted Edwards form, both defined over a special family of finite fields known as Optimal Prime Fields (OPFs). All field-arithmetic operations use a radix-224 representation for the operands (i.e. 24 operand bits are contained in a 32-bit word) to comply with the native (24 ×24)-bit integer multiply instruction of the GT200 platform. We implemented the OPF arithmetic without conditional statements (e.g. if-then clauses) to prevent thread divergence and unrolled the loops to minimize execution time. the scalar multiplication on the twisted Edwards curve employs a comb approach if the base point is fixed and uses extended projective coordinates so that a point addition requires only seven multiplications in the underlying OPF. Our software currently supports elliptic curves over 160-bit and 224-bit OPFs. After a detailed evaluation of numerous implementation options and configurations, we managed to launch 2880 threads on the 30 multiprocessors of the GT200 when the elliptic curve has Montgomery form and is defined over a 224-bit OPF. the resulting throughput is 115k scalar multiplications per second (for arbitrary base points) and we achieved a minimum latency of 19.2 ms. In a fixed-base setting with 256 precomputed points, the throughput increases to some 345k scalar multiplications and the latency drops to 4.52 ms. © 2014 Springer international Publishing.

关键词： Graphics processing unit

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