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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Design and implementation of DMA transfers in WISHBONE interface

Design and implementation of DMA transfers in WISHBONE inter...

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international conference on Communications and Networking in China (CHINACOM)

作者： Lei Lei Jun Wu Tong Sun Songlin Cheng Xin Chen College of Electronic and Information Engineering Tongji University Shanghai China

ISBN: (纸本)9781479987962

the Digital Signal Processor (DSP) is a specialized microprocessor, with its architecture optimized for the operational needs of digital signal *** often uses special memory architectures that are able to fetch multiple data and/or instructions at the same *** applying to WISHBONE bus interface it is much easier to connect the cores, and therefore much easier to create a custom System on Chip (SOC) such as the *** order to increase the data transaction from DSP core to WISHBONE Slave module, this paper proposes a special Direct Memory Access (DMA) which supports a three-ports interface of data transaction. this DMA also offers burst mode and the address list mode of data transaction which can speed the data transmission and make it more flexible. In the process of the design and implement, a synchronization of asynchronous clock issue needs to be solved. the final implementations have been done in ASIC. the functionality of the design is synthesized using Design Compiler and placement and routing by IC compiler.

关键词： Digital signal processing Clocks Registers Synchronization Computer architecture Data communication Delays

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A parallel unpredictable random number generator

A parallel unpredictable random number generator

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Roedunet international conference (RoEduNet)

作者： K. Marton A. Suciu D. Petricean Technical University of Cluj Napoca Romania

Unpredictable random number generators represent a suitable solution when sources of true randomness are not available, too expensive or the nature of the application employing the generator requires a higher throughput and practicality than available TRNGs might provide, but at the same time, the desired level of irreproducibility and unpredictability can not be met by pseudorandom generators. the main goal of the new generator design is to take advantage of the fast randomness generation and different statistical quality of multiple PRNG families and provide an unpredictable combination method, which improves the quality of produced randomness and mitigates certain security problems the individual generators are exposed to if used on their own. Furthermore, the proposed generator leverages the processing power of multi-core and SMP systems by enabling the parallel execution of multiple generators selected by the user's unpredictable mouse movements. the result is a stream of unpredictably combined pseudorandom number sequences which shows high randomness quality - evaluated by the well known NIST statistical test suite, improved by the unpredictability and nondeterminism characteristic to human-computer interaction and doubled by a high generation speed provided by the parallel generation strategy. these characteristics enable the generator to be considered suitable for producing high quality randomness with the promise of cryptographic security.

关键词： Generators Cryptography throughput Mice Lattices NIST

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Extracting Compact Sets of Features for Question Classification in Cognitive Systems: A Comparative Study

Extracting Compact Sets of Features for Question Classificat...

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Marco Pota Angela Fuggi Massimo Esposito Giuseppe De Pietro Institute for High Performance Computing and Networking (ICAR) National Research Council of Italy (CNR) Napoli Italy Institute for High Performance Computing and Networking (ICAR) National Research Council of Italy (CNR) Naples Italy

ISBN: (纸本)9781467394741

Question Classification is one of the key tasks of Cognitive Systems based on the Question Answering paradigm. It aims at identifying the type of the possible answer for a question expressed in natural language. Machine learning techniques are typically employed for this task, and exploit a high number of features extracted from labelled questions of benchmark training sets in order to achieve good classification results. However, the high dimensionality of the feature space often limits the possibility of applying more efficient classification approaches, due to high training costs. In this work, more compact sets of lexical and syntactic features are proposed to distinguish question classes. In particular, the widely used unigrams are substituted with a smaller number of features, extracted by modifying typical Natural Language processing procedures for question analysis. the accuracy values gained on a benchmark dataset by using these different sets of features are compared among them and with the state-of-the-art, taking into account the required complexity at the same time. the new sets of extracted features show a good trade-off between accuracy and complexity.

关键词： Feature extraction Taxonomy Syntactics Aspirin Support vector machines Natural language processing Semantics

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A double boost converter with PFC and series/parallel inputs connection for UPS systems

A double boost converter with PFC and series/parallel inputs...

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IEEE/IAS international conference on Industry Applications (INDUSCON)

作者： José A. L. B. Júnior René P. T. Bascopé Francisco Kleber A. Lima Cícero M. T. Cruz Electrical Engineering Department Energy Processing and Control Group Federal University of Ceará Fortaleza Ceara Brazil

ISBN: (纸本)9781467324120

this paper presents a double boost converter with power factor correction (PFC) suitable for parallel/series connected inputs, depending on the grid voltage value. Using the proposed converter is possible to eliminate the low-frequency autotransformer in input of the converter which allows UPS operation with two input voltage values (110V and 220V). the control strategy is based on the average current mode control and applied to both converters, in order to provide power factor correction and output voltage regulation. the simulation results for a 2.4 kW proposed converter are presented in order to demonstrate the proposed ideas.

关键词： Voltage control Uninterruptible power systems Switches Inductors Inverters Transfer functions Power factor correction

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On the Performance of Apache Hadoop in a Tiny Private IaaS Cloud

On the Performance of Apache Hadoop in a Tiny Private IaaS C...

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international conference on Information Technology: New Generations (ITNG)

作者： Gabriel Loewen Michael Galloway Susan Vrbsky Department of Computer Science The University of Alabama

ISBN: (纸本)9781467359603

High performance and parallel computing are traditionally implemented on very large dedicated compute clusters. However, as many organizations begin to adopt service-oriented cloud-based infrastructures, we can expect to see the development of parallel computing in the cloud. the goal of a parallel compute cluster is to divide a large job into several small jobs, execute the small jobs in parallel on many compute nodes, and then combine the results in some coherent manner. the biggest hurdle in moving this type of service to a cloud-based infrastructure is that performance will undoubtedly be affected by many factors, particularly those related to virtualization in clouds, such as memory and CPU overhead, limited resources, and others relating to hardware virtualization. In order to fully understand how virtualization can affect parallel computing in a tiny private cloud, we have devised four case studies that examine the performance of Apache Hadoop in varying environments on our private cloud. Our case studies are comprised of a baseline or bare metal (non-virtualized) cluster deployment consisting of seven nodes, a seven-node virtual machine cluster, a twenty-node virtual machine cluster, and an optimized seven-node virtual machine cluster. Results show that, although small data sets result in comparable job completion times, as the data size increases the performance of Apache Hadoop is affected greatly by virtualization even when we attempt to optimize the configuration of our cloud.

关键词： Virtual machining Cloud computing Virtualization Metals Hardware parallel processing Organizations

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An intelligent system for accelerating parallel SVM classification problems on large datasets using GPU

An intelligent system for accelerating parallel SVM classifi...

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international conference on Intelligent Systems Design and Applications (ISDA)

作者： Qi Li Raied Salman Vojislav Kecman Department of Computer Science Virginia Commonwealth University Richmond USA

Support Vector Machine (SVM) is one of the most popular tools for solving general classification and regression problems because of its high predicting accuracy. However, the training phase of nonlinear kernel based SVM algorithm is a computationally expensive task, especially for large datasets. In this paper, we propose an intelligent system to solve large classification problems based on parallel SVM. the system utilizes the latest powerful GPU device to improve the speed performance of SVM training and predicting phases. the memory constraint issue brought by large datasets is addressed through either data reduction or data chunking techniques. the complete system includes multiple executable modules and all of them are managed through a main script, which reduces the implementation difficulty and offers platform portability. Empirical results have shown that our system achieves an order of magnitude speed up compared to the classic SVM tool, LIBSVM. the speed performance is further improved to two orders of magnitude by slightly compromising on the predicting accuracy.

关键词： Support vector machines Training Graphics processing unit Accuracy Intelligent systems Kernel Testing

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Evaluating the Soft Error Resilience of Graph Applications on GPGPUs

Evaluating the Soft Error Resilience of Graph Applications o...

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IEEE international conference on Big Data Security on Cloud (BigDataSecurity), High Performance and Smart Computing (HPSC) and Intelligent Data and Security (IDS)

作者： Xiaohui Wei Mengting Zhou Nan Jiang Hengshan Yue College of Computer Science and Technology Jilin University Changchun China

ISBN: (数字)9798350389524

ISBN: (纸本)9798350389531

General-Purpose Graphics processing Units (GPGPUs) are widely utilized for graph processing thanks to their high throughput, massive parallelism and powerful computing capacity. However, due to the increasing integration, GPGPUs are susceptible to soft errors, which can undermine the reliability of graph applications accelerated using GPGPUs. Typically, fault tolerance strategies such as thread replication and checkpoint mechanism are applied to ensure the reliability of program execution. However, these techniques require appropriate trade-off between reliability improvement and overhead. To this end, it is imperative to understand the error resilience profile of graph applications. In this paper, we construct a multidimensional analysis framework, which analyzes the error resilience of graph applications on GPGPUs from application, kernel function, and thread perspective. Based on the exhaustive statistical fault injection (FI) results for four graph algorithms, we propose heuristic suggestions as guidance for efficient fault tolerance strategies.

关键词： Fault tolerance Instruction sets Heuristic algorithms Fault tolerant systems Graphics processing units parallel processing throughput

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Data placement and buffer management for concurrent mergesorts with parallel prefetching

Data placement and buffer management for concurrent mergesor...

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international conference on Data Engineering

作者： Kun-Lung Wu P.S. Yu J.Z. Teng IBM Thomas J. Watson Research Center Yorktown Heights NJ USA IBM Programming Systems Toronto Laboratory San Jose CA USA

ISBN: (纸本)0818654023

Various data placement policies are studied for the merge phase of concurrent mergesorts using parallel prefetching, where initial sorted runs (input) of a merge and its final sorted run (output) are stored on multiple disks but each run resides only on a single disk. Since the merge phase involves only sequential references, parallel prefetching can be attractive an reducing the average response time for concurrent merges. However, without careful buffer control, severe thrashing may develop under certain run placement policies, reducing the benefits of prefetching. the authors examine through detailed simulations three different run placement policies. the results show that even though buffer thrashing can be almost avoided by placing the output run of a job on the same disk with at least one of its input runs, this thrashing-avoiding run placement policy can be substantially outperformed by other policies that use buffer thrashing control. With buffer thrashing avoidance, the best performance as achieved by a run placement policy that uses a proper subset of disks dedicated for writing the output runs while the rest of the disks are used for prefetching the input runs in parallel.< >

关键词： Prefetching Delay Writing throughput Sorting Databases Query processing

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A scaled autonomous vehicle platform to develop and investigate driver assistance and control algorithm

A scaled autonomous vehicle platform to develop and investig...

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IEEE international Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications

作者： Alexander Kuznietsov University of applied Sciences Mittelhessen Friedberg Germany

this paper describes an intelligent 1:10 scaled vehicle. the car possesses the capability to drive autonomously performing several typical maneuvers like parallel parking, lane keeping, obstacle detection and avoidance. the developed platform can be utilized for developing and testing of new vehicle control algorithms as well as for teaching purposes.

关键词： Vehicles Sensors Mobile robots Signal processing algorithms Vehicle dynamics Heuristic algorithms Algorithm design and analysis

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Performance optimization of Histogram Equalization for digital images using modern imaging

Performance optimization of Histogram Equalization for digit...

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international conference on Computing and Networking Technology (ICCNT)

作者： G Kalyan Kumar Anita Titus R.S. Vijayashanthi M Shalini M Dinesh Department of CSE Rajalakshmi Institute of Technology Chennai Department of ECE Jeppiaar University Chennai Department of ECE S.A. Engineering College Chennai Department of CSE St. Joseph’s College of Engineering Chennai Department of VLSI Microelectronics Saveetha School of Engineering Saveetha Institute of Medical and Technical Sciences (SIMATS) Saveetha University Chennai

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Histogram equalization is a method of contrast adjustment in image processing using the image’s histogram. However, as modern imaging systems become more complex, these traditional algorithms for histogram equalization are no longer efficient. In response to this problem, researchers have studied several strategies for improving the performance of histogram equalization in digital images. An option is to use parallel processing and multi-threading approaches to distribute the computational burden, thereby speeding up the execution of histogram equalization. Another methodology includes using machine learning algorithms to adapt histogram equalization parameters according to the input image. Furthermore, using advanced hardware architectures like Field Programmable Gate Arrays (FPGA), Graphic processing Units (GPU), or Application Specific Integrated Circuits can significantly enhance the speed and efficiency of a Histogram Equalization. the performance optimization techniques have provided encouraging results, which significantly refine image processing time and visual perception. Modern imaging systems may benefit tremendously from their use in the new age.

关键词： Histograms Machine learning algorithms Digital images Surveillance Graphics processing units parallel processing Real-time systems Optimization Field programmable gate arrays Visual perception

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