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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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A high throughput, low latency null convention logic 16×16-bit multiplier

A high throughput, low latency null convention logic 16×16-...

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international conference on Signal processing and Communication Systems, ICSPCS

作者： Prashant Dabholkar Paul Beckett School of Engineering RMIT University

ISBN: (纸本)9781509009428

Digital signal processing is at the heart of modern personal communication devices that support high throughput media streams. Although DSPs are typically implemented using high performance clocked processors, delay-insensitive asynchronous techniques are being increasingly applied as they are robust to the extreme variability of modern nano-scale fabrication processes. As an additional benefit, these systems do not exhibit the trade off between latency and throughput that is a characteristic of clocked Boolean systems. In this paper, a low latency Null Convention Logic based parallel 16×16 bit multiplier is used to illustrate the pipelining behaviour in an NCL system. We show that a 16×16 non-pipelined NCL multiplier achieves a throughput of nearly 260 Mops/sec, with a latency of around 1.20 ns. By including 15 pipeline stages, the multiplier throughput can be more than doubled to 609 Mops/sec while the latency increases to only 2.26 ns. this can be contrasted with the corresponding synchronous multiplier incorporating the same number of pipeline stages, which would exhibit a latency of around 25 ns at an equivalent throughput.

关键词： nanofabrication Boolean functions digital signal processing chips logic circuits multiplying circuits Multiplying circuits digital signal processing chips Latency Logic circuits Boolean functions Nanofabrication throughput Null convention logic Fabrication process

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A Configurable Detector Based on Layered Belief Propagation for Massive MIMO Detection

A Configurable Detector Based on Layered Belief Propagation ...

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international conference on Integrated Circuits and Microsystems (ICICM)

作者： Rui Gao Houren Ji Wenyue Zhou Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS) National Mobile Communications Research Laboratory Southeast University Nanjing China Purple Mountain Laboratories Nanjing China

Massive multiple-input multiple-output (MIMO) detection plays a prominent role in the field of wireless communication. And with this trend, message passing detection (MPD) attracts a great attention since its advantages of high throughput and low complexity between distinct detection algorithms. Among various MPD algorithms, Gaussian approximate interference belief propagation (GAI-BP) detection can exhibit excellent convergence and performance in the different scenarios. However, its hardware design should be more efficient and flexible further. this paper proposes a novel semi-parallel hardware architecture for GAI-BP detection, aimed at improving its configurability using a layer scheduling scheme. through this scheme, the proposed detector achieves a gain of 0.65 dB when compared to the original algorithm, while simultaneously accommodating multi-antenna radios through the proposed hardware design.

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Quadratic Mutual Information estimation of mouse dLGN receptive fields reveals asymmetry between ON and OFF visual pathways

Quadratic Mutual Information estimation of mouse dLGN recept...

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international IEEE/EMBS conference on Neural Engineering, CNE

作者： Zhiguang Mu Konstantin Nikolic Simon R. Schultz Neural Computation Unit Okinawa Institute of Science and Technology Okinawa Japan Imperial College London London Centre for Neurotechnology Imperial College London London

ISBN: (纸本)9781728143378;9781728143385

the longstanding theory of “parallel processing” predicts that, except for a sign reversal, ON and OFF cells are driven by a similar pre-synaptic circuit and have similar visual field coverage, direction/orientation selectivity, visual acuity and other functional properties. However, recent experimental data challenges this view. Here we present an information theory based receptive field (RF) estimation method - quadratic mutual information (QMI) - applied to multi-electrode array electrophysiological recordings from the mouse dorsal lateral geniculate nucleus (dLGN). this estimation method provides more accurate RF estimates than the commonly used Spike-Triggered Average (STA) method, particularly in the presence of spatially correlated inputs. this improved efficiency allowed a larger number of RFs (285 vs 189 cells) to be extracted from a previously published dataset. Fitting a spatial-temporal Difference-of-Gaussians (ST-DoG) model to the RFs revealed that while the structural RF properties of ON and OFF cells are largely symmetric, there were some asymmetries apparent in the functional properties of ON and OFF visual processing streams - with OFF cells preferring higher spatial and temporal frequencies on average, and showing a greater degree of orientation selectivity.

关键词： Radio frequency Visualization Fitting Estimation Neural engineering parallel processing Mice

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Human centricity and perception-based perspective of architectures of Granular Computing

Human centricity and perception-based perspective of archite...

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IEEE international conference on Cognitive Informatics

作者： Witold Pedrycz Systems Research Institute Polish Academy of Sciences Warsaw Poland Department of Electrical & Computer Engineering University of Alberta Edmonton Canada

In spite of their striking diversity, numerous tasks and architectures of intelligent systems such as those permeating multivariable data analysis (e.g., time series, spatio-temporal, and spatial dependencies), decision-making processes along with their models, recommender systems and others exhibit two evident commonalities. they promote human centricity and vigorously engage perceptions (rather than plain numeric entities) in the realization of the systems and their usage. Information granules play a pivotal role in such settings. In the sequel, Granular Computing delivers a cohesive framework supporting a formation of information granules and facilitating their processing. We exploit two essential concepts of Granular Computing. the first one, formed with the aid of a principle of justifiable granularity, deals with the construction of information granules. the second one, based on an idea of an optimal allocation of information granularity, helps endow constructs of intelligent systems with a very much required conceptual and modeling flexibility. the talk covers in detail two representative studies. the first one is concerned with a granular interpretation of temporal data where the role of information granularity is profoundly visible when effectively supporting human centric description of relationships existing in data. In the second study being focused on the Analytic Hierarchy Process (AHP) used in decision-making, we show how an optimal allocation of granularity helps facilitate collaborative activities (e.g., consensus building) in group decision-making.

关键词： Helium

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Mapping and scheduling for architecture exploration of networking SoCs

Mapping and scheduling for architecture exploration of netwo...

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international conference on VLSI Design

作者： T. Wild J. Foag N. Pazos W. Brunnbauer Institute for Integrated Circuits Technical University Munich Munich Germany System Architecture Group Communications Infineon Technologies North America Corporation San Jose CA USA

Describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture under special consideration of on-chip communications. A constructive algorithm is presented that extends previous work by taking into account potential data transfers in the future. the second approach is a recursive procedure that is based on local search techniques in a specially defined neighborhood of the critical path. Simulated annealing and tabu search are used as search algorithms. Both approaches find solutions with better performance than established methodologies. the recursive technique leads to superior results than the constructive approach, however, is limited to small and mid-sized problems, whereas the constructive algorithm is not limited by this issue.

关键词： Scheduling Partitioning algorithms Very large scale integration Delay NP-complete problem Polynomials Constraint optimization parallel processing Proposals Context

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A Heterogeneous KBA parallel Algorithm for the Cartesian Discrete Ordinates for Multizone Heterogeneous System

A Heterogeneous KBA Parallel Algorithm for the Cartesian Dis...

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international conference on Computers, Communications, and Systems (ICCCS)

作者： Runhua Li Jie Liu Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

Innovations in powerful high-performance computing (HPC) architecture are enabling high-fidelity whole-core neutron transport simulations at reasonable time. Especially, the currently fashionable heterogeneous architectures make the cost of such simulations at very low level. Neutron distribution of a reactor core is governed by the Boltzmann neutron transport equation (BTE), first viable solutions of which need tremendous computer resources. Among of the high-fidelity numerical methods, the discrete ordinates method (SN) is becoming popular in the reaction design community by taking a good balance between computational cost and accuracy. Recently, MT-3000, which is a multizone heterogeneous architecture with a peak double precision performance of 11.6 TFLOPS, is proposed. In this work, the BTE is solved by the SN with heterogenous Koch-Baker-Alcouffe (KBA) parallel algorithms based on the MT-3000 architecture. A communication mechanism has been established to efficiently transmit data among the acceleration cores and the CPU cores. the kernel computation procedure is largely accelerated by the vectorization and instruction pipelining techniques. Numerical experiments show that our formulation could achieve 1.37 TFLOPs with single MT-3000, that is 11.8% of its peak performance.

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An Optimized Tag Sorting Circuit in WFQ Scheduler Based on Leading Zero Counting

An Optimized Tag Sorting Circuit in WFQ Scheduler Based on L...

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2010 10th IEEE international conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Xiao-Ping Huang Xiao-Ya Fan Sheng-Bing Zhang Fan Zhang Computer School Northwestern Polytechnical University Xian 710072 China

the tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. the architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the traditional comparator-tree-based architecture, it can improve the frequency by 15％ and reduce the area by 22％.

关键词： Computer architecture Sorting Quality of service Hardware Logic gates Field programmable gate arrays Pipeline processing

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Optimize hardware with fixed-point variable length phase factors

Optimize hardware with fixed-point variable length phase fac...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Todd E. Schmuland Mohsin M. Jamali Matthew B. Longbrake Peter E. Buxa Department of Electrical Engineering & Computer Science The University of Toledo Toledo OH AFRL/RYDR Wright-Patterson AFB Dayton OH

Fast Fourier Transforms (FFTs) are highly parallel in nature and consist of simple addition, subtraction, and complex rotation operators with phase factors (a.k.a. twiddle factors). With the advent of FPGAs and other reconfigurable seas-of-logic, it is now possible to construct a fully parallel FFT structure where the phase factors are now constants and good targets for hardware optimization. By varying the fixed-point length of the phase factors using phase angle error percentage as a control for the variable length phase factor quantizer, the number of shifted adders required to implement the complex rotation operators can be reduced. Performance comparisons of fixed length and variable length phase factors, along with two quantizer rounding modes, are investigated.

关键词： Adders Hardware Field programmable gate arrays Optimization Digital signal processing Quantization Fourier transforms

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Fast software implementation of MPEG advanced audio encoder

Fast software implementation of MPEG advanced audio encoder

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international conference on Digital Signal processing (DSP)

作者： I. Dimkoviae D. Milovanoviae Z. Bojkoviae PsyTEL Research Belgrade Serbia Faculty of Elcclrical Engineering Belgrade Serbia

An optimized software implementation of a high quality MPEG AAC-LC (low complexity) audio encoder is presented in this paper. the standard reference encoder is improved by utilizing several algorithmic optimizations (fast psycho-acoustic model, new tonality estimation, new time domain block switching, optimized quantizer and Huffman coder) and very careful code optimizations for PC CPU architectures with SIMD (single-instruction-multiple-data) instruction set. the psychoacoustic model used the MDCT filterbank for energy estimation and peak detection as a measure of tonality. Block size decision is based on local perceptual entropies as well as LPC analysis of the time signal. Algorithmic optimizations in the quantizer include loop control module modification and optimized Huffman search. Code optimization is based on parallel processing by replacing vector algebra and math junctions with their optimized equivalents with Intel/sup /spl reg// Signal processing Library (SPL). the implemented codec outperforms consumer MP3 encoders at 30% less bitrate at the same time achieving encoding times several times faster than real-time.

关键词： Signal processing algorithms Psychoacoustic models Software quality Code standards Psychology Filter bank Energy measurement Entropy Linear predictive coding Signal analysis

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An FPGA implementation of 3D affine transformations

An FPGA implementation of 3D affine transformations

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： F. Bensaali A. Amira I.S. Uzun A. Ahmedsaid School of Computer Science Queen''s University Belfast UK

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. this paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.

关键词： Field programmable gate arrays Computer graphics Costs parallel processing Application software Acceleration Hardware design languages Computer science Computer applications Design automation

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