检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,682 篇 会议
56 册 图书
54 篇 期刊文献

馆藏范围

2,792 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,839 篇 工学
- 1,626 篇 计算机科学与技术...
- 845 篇 软件工程
- 338 篇 电气工程
- 220 篇 电子科学与技术（可...
- 208 篇 信息与通信工程
- 84 篇 控制科学与工程
- 62 篇 光学工程
- 57 篇 机械工程
- 41 篇 仪器科学与技术
- 38 篇 生物医学工程（可授...
- 38 篇 生物工程
- 31 篇 材料科学与工程（可...
- 25 篇 动力工程及工程热...
- 21 篇 化学工程与技术
- 20 篇 建筑学
- 15 篇 土木工程
- 13 篇 力学（可授工学、理...
- 12 篇 交通运输工程
499 篇 理学
- 342 篇 数学
- 113 篇 物理学
- 51 篇 系统科学
- 48 篇 生物学
- 30 篇 统计学（可授理学、...
- 26 篇 化学
173 篇 管理学
- 119 篇 管理科学与工程(可...
- 62 篇 图书情报与档案管...
- 49 篇 工商管理
40 篇 医学
- 30 篇 临床医学
- 14 篇 基础医学(可授医学...
15 篇 法学
- 15 篇 社会学
9 篇 经济学
9 篇 农学
8 篇 文学
2 篇 军事学
1 篇 教育学

主题

360 篇 parallel process...
219 篇 computer archite...
205 篇 graphics process...
146 篇 parallel archite...
135 篇 graphics process...
129 篇 hardware
115 篇 parallel algorit...
112 篇 image processing
98 篇 computational mo...
94 篇 concurrent compu...
87 篇 instruction sets
86 篇 field programmab...
83 篇 algorithm design...
79 篇 multicore proces...
77 篇 signal processin...
76 篇 parallel process...
66 篇 parallel program...
60 篇 gpu
59 篇 throughput
59 篇 kernel

机构

11 篇 natl univ def te...
6 篇 college of compu...
6 篇 school of comput...
6 篇 hosei univ dept ...
6 篇 natl univ def te...
5 篇 univ aizu dept c...
5 篇 carleton univ sc...
5 篇 school of comput...
5 篇 computer science...
5 篇 city university ...
4 篇 chinese acad sci...
4 篇 univ michigan ad...
4 篇 institute of com...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 univ jaume 1 dep...
4 篇 hainan internati...
4 篇 tech univ cluj n...
4 篇 department of co...
4 篇 beihang universi...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
9 篇 konrad karczewsk...
9 篇 quintana-orti en...
7 篇 dongarra jack
7 篇 kothapalli kisho...
6 篇 hannig frank
6 篇 liu jie
6 篇 su jinshu
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wyrzykowski roma...
6 篇 thulasiraman par...
5 篇 ito yasuaki
5 篇 jerzy waśniewski
5 篇 wang guojun
5 篇 geyong min
5 篇 wanlei zhou

语言

2,756 篇 英文
14 篇 中文
11 篇 俄文
11 篇 其他
2 篇 乌克兰文
1 篇 西班牙文

检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是2581-2590 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Meta-programming and Multi-stage Programming for GPGPUs

Meta-programming and Multi-stage Programming for GPGPUs

引用

IEEE international Symposium on Embedded Multicore Socs (MCSoC)

作者： Ian Masliah Marc Baboulin Joel Falcou University Paris Sud Orsay France

ISBN: (纸本)9781509035328

GPGPUs and other accelerators are becoming a mainstream asset for high-performance computing. Raising the programmability of such hardware is essential to enable users to discover, master and subsequently use accelerators in day-to-day simulations. Furthermore, tools for high-level programming of parallel architectures are becoming a great way to simplify the exploitation of such systems. For this reason, we have extended NT2 - the Numerical Template Toolbox - a C++ scientific computing library which can generate code for SIMD and multithreading systems in a transparent way using a MATLAB like syntax. In this paper, we study how to introduce an accelerator based programming model into this library to allow developers to reap the benefits of such an architecture. After a brief description of the NT2 framework, we explain how our accelerator programming model has been designed and integrated in a pure C++ library. We conclude by showing the applicability and performance of this tool on some practical applications.

关键词： Libraries C++ languages Graphics processing units Programming Computational modeling MATLAB Mathematical model

来源：评论

学校读者我要写书评

暂无评论

DASH: Dynamic Scheduling Algorithm for Single-ISA Heterogeneous Nano-scale Many-Cores

DASH: Dynamic Scheduling Algorithm for Single-ISA Heterogene...

引用

international econference on Computer and Knowledge Engineering (ICCKE)

作者： Keihaneh Kia Amir Rajabzadeh Engineering faculty Razi University Kermanshah Iran

ISBN: (数字)9781728185668

ISBN: (纸本)9781728185675

the difference in the performance of identical cores due to the process variation and the different distance of cores from the shared last level cache (LLC) besides power limitation should be considered in scheduling algorithms to exploit the maximum performance of the Nano-scale many-core processors. this paper presents a dynamic heuristic scheduling algorithm, called DASH, to maximize performance under the mentioned challenges. In this regard, we estimate the execution time of each task of a job on a core as a relation of frequency and the communication cost of the core, as well as the type of the job and its tasks. According to this estimation model DASH selects some cores to maximize performance while exploiting DVFS to reduce the effect of power limitation. the time overhead of our algorithm is compatible with dynamic systems. We evaluate DASH by running random sequences of jobs from SPLASH parallel benchmark suite in Sniper and MACPat simulator for performance and power estimation. the results show that the throughput of DASH is 7.1% and 30.4% more than two similar algorithms.

关键词： Program processors Task analysis Multicore processing Heuristic algorithms Scheduling algorithms Estimation Dynamic scheduling

来源：评论

学校读者我要写书评

暂无评论

Mobility and mobility management: a conceptual framework

Mobility and mobility management: a conceptual framework

引用

IEEE international conference on Networks

作者： Jun-Zhao Sun J. Sauvola MediaTeam Machine Vision and Media Processing Unit Infotech Oulu University of Oulu Oulu Finland

ISBN: (纸本)0780375335

the tremendous demands from the social market are pushing the development of mobile communications faster than ever before, leading to the emergence of many new techniques. Within those techniques, mobility management has widely been recognized as one of the most important problems for seamless access to wireless networks and services. this paper proposes a conceptual framework for mobility and mobility management, with the emphasis on the key research issues involved in the effort to design graceful mobility management schemes. the effects of mobility on both the architectures and protocols of networks and communications are presented. Diversity of the future mobile communication systems introduces new challenges, which lead to the definitions of mobility on various levels according to different granularities. Mobility management is defined as two complementary operations, i.e. location management and handoff management. the paper also describes mobility management issues at the network layer. the processing stages of the two operations are introduced, together with the analyses of key research issues and possible solutions. Finally, we discuss issues concerning the performance evaluation of mobility management schemes.

关键词： Mobile radio mobility management Mobile communication Wireless networks Access protocols Mobile computing 3G mobile communication Roaming Sun Machine vision Bandwidth

来源：评论

学校读者我要写书评

暂无评论

parallel Combinatory Spread Spectrum System Based on Single Carrier Frequency Domain Equalization in Multipath Fading Channels

Parallel Combinatory Spread Spectrum System Based on Single ...

引用

Communication, Image and Signal processing (CCISP), international conference on

作者： Liu Yang Dan Ding Zhicheng Shen Liming Hu Hao Chen Department of Electric and Optical Engineering Space Engineering University of PLA Beijing China 10th detachment 78156th Unit of PLA Chengdu China Graduate School Space Engineering University of PLA Beijing China

To solve the problem of performance limitation of direct sequence (DS) spread spectrum system in complex multipath environment, a parallel combinatory spread spectrum (PCSS) framework that combines single carrier frequency domain equalization (SCFDE) is proposed. Higher data rates and large processing gain can be achieved by PCSS transmission and the frequency-selective fading is overcome by frequency domain equalization, which is easy to implement at the receiver for the benefit of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT). Moreover, in order to balance the transmission rate and reliability in different environments and tasks, an improved PCSS framework with adaptive processing gain is investigated by deploying variable spread spectrum factors under the condition that the number of FFT/IFFT processing points is fixed, by which the control logic is very simple and it is convenient for real implementation. Experimental results demonstrate that the proposed PCSS schemes based on SCFDE show good performance in overcoming multipath fading. In the meanwhile, higher bandwidth utilization can be obtained compared with traditional DS strategy.

关键词：

来源：评论

学校读者我要写书评

暂无评论

De(con) Struction of the Lazy-F Loop: Improving Performance of Smith Waterman Alignment

De(con) Struction of the Lazy-F Loop: Improving Performance ...

引用

IEEE Symposium on Bioinformatics and Bioengineering (BIBE)

作者： Roman Snytsar Research and AI Microsoft Redmond USA

ISBN: (纸本)9781728146188

Striped variation of the Smith-Waterman algorithm is known as extremely efficient and easily adaptable for the SIMD architectures. However, the potential for improvement has not been exhausted yet. the popular Lazy-F loop heuristic requires additional memory access operations, and the worst-case performance of the loop could be as bad as the nonvectorized version. We demonstrate the progression of the lazy-F loop transformations that improve the loop performance, and ultimately eliminate the loop completely. Our algorithm achieves the best asymptotic performance of all scan-based SW algorithms O(n/p+log(p)), and is very efficient in practice.

关键词： Bioinformatics parallel processing Optimization Arrays Computational complexity Instruction sets

来源：评论

学校读者我要写书评

暂无评论

Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Design and Verification of High-Speed Radix-2 Butterfly FFT ...

引用

international conference on Trends in Electronics and Informatics (ICEI)

作者： Utsav Kumar Malviya Government Engineering College Bilaspur India

ISBN: (数字)9781728155180

ISBN: (纸本)9781728155197

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). this work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). the operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. this work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2 2 had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. this work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.

关键词： Adders Random access memory Pipeline processing conferences Market research Informatics Digital signal processing

来源：评论

学校读者我要写书评

暂无评论

Latency Hiding in Multi-threading and Multi-processing of Network Applications 07

Latency Hiding in Multi-Threading and Multi-Processing of Ne...

引用

international conference on parallel Architecture and Compilation Techniques (PACT)

作者： Xiaofeng Guo Jinquan Dai Long Li Zhiyuan Lv Prashant R. Chandra Google Inc. USA Intel China Software Center China Intel Corporation USA

ISBN: (纸本)9780769529448

Network processors employ a multithreaded, chip-multiprocessing architecture to effectively hide memory latency and deliver high performance for packet processing applications. In such a parallel paradigm, when multiple threads modify a shared variable in the external memory, the threads should be properly synchronized such that the accesses to the shared variable are protected by critical sections. therefore, in order to efficiently harness the performance potential of network processors, it is critical to hide the memory latency and synchronization latency in multi-threading and multiprocessing. In this paper, we present a novel program transformation used in the Intelreg Auto-partitioning C Compiler for IXP, which perform optimal placement of memory access instructions and synchronization instructions for effective latency hiding. Experimental results show that the transformation provides impressive speedup (up-to to 8.5x) and scalability (up- to 72 threads) of the performance for the real-world network application (a 10Gbps Ethernet Core/Metro Router).

关键词： Delay Program processors Yarn Application software Random access memory Protection Scalability Optimizing compilers parallel architectures Programming

来源：评论

学校读者我要写书评

暂无评论

Using HPX and OP2 for Improving parallel Scaling Performance of Unstructured Grid Applications

Using HPX and OP2 for Improving Parallel Scaling Performance...

引用

international conference on parallel processing Workshops (ICPPW)

作者： Zahra Khatami Hartmut Kaiser J. Ramanujam The STE∥AR Group Baton Rouge Louisiana USA Center for Computation and Technology Louisiana State University

ISBN: (纸本)9781509028269

Computer scientists and programmers face the difficultly of improving the scalability of their applications while using conventional programming techniques only. As a base-line hypothesis of this paper we assume that an advanced runtime system can be used to take full advantage of the available parallel resources of a machine in order to achieve the highest parallelism possible. In this paper we present the capabilities of HPX - a distributed runtime system for parallel applications of any scale - to achieve the best possible scalability through asynchronous task execution [1]. OP2 is an active library which provides a framework for the parallel execution for unstructured grid applications on different multi-core/many-core hardware architectures [2]. OP2 generates code which uses OpenMP for loop parallelization within an application code for both single-threaded and multi-threaded machines. In this work we modify the OP2 code generator to target HPX instead of OpenMP, i.e. port the parallel simulation backend of OP2 to utilize HPX. We compare the performance results of the different parallelization methods using HPX and OpenMP for loop parallelization within the Airfoil application. the results of strong scaling and weak scaling tests for the Airfoil application on one node with up to 32 threads are presented. Using HPX for parallelization of OP2 gives an improvement in performance by 5%-21%. By modifying the OP2 code generator to use HPX's parallel algorithms, we observe scaling improvements by about 5% as compared to OpenMP. To fully exploit the potential of HPX, we adapted the OP2 API to expose a future and dataflow based programming model and applied this technique for parallelizing the same Airfoil application. We show that the dataflow oriented programming model, which automatically creates an execution tree representing the algorithmic data dependencies of our application, improves the overall scaling results by about 21% compared to OpenMP. Our results show

关键词： Automotive components parallel processing Scalability Programming Instruction sets Runtime Hardware

来源：评论

学校读者我要写书评

暂无评论

Implementation of parallel sparse Cholesky factorization on GPU

Implementation of parallel sparse Cholesky factorization on ...

引用

international conference on Computer Science and Network Technology (ICCSNT)

作者： Dan Zou Yong Dou National Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781467329637

Direct methods for solving large sparse symmetric positive-definite linear systems of equations are popular because of their generality and robustness. the main bottleneck is the sparse Cholesky factorization, which exhibits irregular memory access behavior and unbalanced workload. In the past 10 years, many sparse Cholesky factorization algorithms have emerged, exploiting new architectural features. However, programming techniques currently employed on these platforms are not sufficient to implement sparse Cholesky factorization on many-core graphics processing units (GPUs) due to mismatches between irregular problem structures and single-instruction multiple-thread GPU architectures. In the present paper, we propose a task-based software approach for the parallel sparse Cholesky factorization aimed at heterogeneous computing platforms with GPU accelerators. the tasks are generated by CPU. An efficient task-scheduling mechanism guarantees the correct ordering of task execution and ensures a load balanced execution on GPU. Comparisons are made with the existing solver using problems arising from a range of practical applications. the experiment results show that the proposed approach can substantially improve the performance of sparse Cholesky factorization on GPU with 2.7×-4× speedup.

关键词： Sparse Cholesky factorization GPU Cholesky factorisation Graphics processing Unit GRAPPER PICK UP Task execution

来源：评论

学校读者我要写书评

暂无评论

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

Oversampled multi-phase time-domain bit-error rate processin...

引用

Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Rozita Najafi Carle Banville Mohamed Hafed Zeljko Zilic Department of Electrical and Computer Engineering McGill University Montreal QUE Canada DFT MicroSystems Inc. Montreal Canada

this paper investigates techniques to speed up HSSI bit-error rate (BER) and jitter testing. the proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). parallel BERT elements are able to digitize the input signal jitter behavior in a multi-phase manner. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.

关键词： Bit error rate Jitter Delay Synchronization Transmitters Discrete Fourier transforms

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共280页 << < 255 256 257 258 259 260 261 262 263 264 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：