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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是2611-2620 订阅

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Investigating parallelization of Cross-language Plagiarism Detection System Using the Winnowing Algorithm in Cloud Based Implementation

Investigating Parallelization of Cross-language Plagiarism D...

引用

IEEE international conference on Awareness Science and Technology

作者： Anak Agung Putri Ratna F. Astha Ekadiyanto Ihsan Ibrahim Diyanatul Husna Fathimah Rahimullah Department of Electrical Engineering Faculty of Engineering Universitas Indonesia Depok Indonesia

the computational performance of cross-language plagiarism detection system using winnowing algorithm developed at the Electrical Engineering Department, Universitas Indonesia became an issue for real world application. this research is investigating the parallelization of such system implemented on a lab-scale multicore based private cloud platform using OpenStack. parallelization was done on the portion of the program where the paragraphs of reference documents are processed. the result of execution time of the overall parallelized computation was able to reach speed up of 1.07 to 3.52 times compared to the execution time of the original serial computation.

关键词： Cloud computing Plagiarism Multiprocessing systems Python parallel processing

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Retargetable Communication for Distributed Programs

Retargetable Communication for Distributed Programs

引用

international ACM SIGSOFT conference on Quality of Software architectures (QoSA)

作者： Oren Freiberg Jens Palsberg Mahdi Eslamimehr Microsoft Viewpoints Research Institute

ISBN: (纸本)9781509025688

the emergence of clusters of multi-core multiprocessors has created a challenge for software developers who use concurrency to gain performance. the challenge lies in the application's dependence on both the hardware and the deeply integrated communication infrastructure for performance improvements. this integration of the communication and parallelism in the user's application reduces flexibility by adding complexity when switching to different communication and parallel infrastructures. In this paper, we present a retargetable compiler framework for a subset of X10 that abstracts the hardware details, parallelism, and communication away from the application, allowing for portability and easier retargeting of the communication and parallelism. the retargetable compiler framework uses asynchronous computation and communication, as well as the concept of places to abstract away hardware details and to provide scalability. the framework offers performance, functionality, and flexibility because of our separation of tasks into layers and because of source code level serialization. To illustrate the ease of retargeting the communication and the patterns of parallelism, our framework is implemented with two different communication APIs (DUP and MPI-2) and two different patterns of parallelism (thread pooling and thread spawning). Retargeting the communication infrastructure using our framework required fewer code changes than changing the pattern of parallelism. the minimal code change needed to retarget these components offers developers a reasonable way to retarget without recompiling their application or sacrificing performance.

关键词： Message systems parallel processing Libraries Hardware Benchmark testing Switches Synchronization

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Optimisation and parallelism in synchronous digital circuit simulators

Optimisation and parallelism in synchronous digital circuit ...

引用

IEEE international conference on Computational Science and Engineering, CSE

作者： M. Chimeh Cordelia V. Hall John T. O'Donnell Sch. of Comput. Sci. Univ. of Glasgow Glasgow UK School of Computing Science University of Glasgow Glasgow UK University of Glasgow Glasgow Glasgow GB

Digital circuit simulation often requires a large amount of computation, resulting in long run times. We consider several techniques for optimising a brute force synchronous circuit simulator: an algorithm using an event queue that avoids recalculating quiescent parts of the circuit, a marking algorithm that is similar to the event queue but that avoids a central data structure, and a lazy algorithm that avoids calculating signals whose values are not needed. Two target architectures for the simulator are used: a sequential CPU, and a parallel GPGPU. the interactions between the different optimisations are discussed, and the performance is measured while the algorithms are simulating a simple but realistic scalable circuit.

关键词： Registers Arrays Integrated circuit modeling Clocks Graphics processing units Force Optimization

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A High-Performance Hardware Architecture for Spectral Hash Algorithm

A High-Performance Hardware Architecture for Spectral Hash A...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Ray C.C. Cheung Çetin K. Koc John D. Villasenor City University of Hong Kong Hong Kong China Electrical Engineering Department UCLA Los Angeles CA USA Computer Science Department University of California슠Santa Barbara Santa Barbara CA USA

the spectral hash algorithm is one of the round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete Fourier transformations over a finite field, data dependent permutations, rubic-type rotations, and affine and nonlinear functions. the underlying mathematical structures and operations pose interesting and challenging tasks for computer architects and hardware designers to create fast, efficient, and compact ASIC and FPGA realizations. In this paper, we present an efficient hardware architecture for the full 512-bit hash computation using the spectral hash algorithm. We have created a pipelined implementation on a Xilinx Virtex-4 XC4VLX200-11 FPGA which yields 100 MHz and occupies 38,328 slices, generating a throughput of 51.2 Gbps. Our fully parallel synthesized implementation shows that the spectral hash algorithm is about 100 times faster than the fastest SHA-1 implementation, while requiring only about 13 times as many logic slices.

关键词： Hardware Galois fields Signal processing algorithms Elliptic curve cryptography Discrete Fourier transforms Arithmetic Computer architecture Field programmable gate arrays Power engineering computing NIST

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A Fast parallel Algorithm Based on GPU for Harmonic Balance Method

A Fast Parallel Algorithm Based on GPU for Harmonic Balance ...

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IEEE Asia-Pacific conference on Antennas and Propagation (APCAP)

作者： Zhengzhuo Wang Yanliang Sha Lingyun Ouyang Quan Chen Jianguo Hu School of Microelectronics Science and Technology Sun Yat-sen University Zhuhai China School of Microelectronics Southern University of Science and Technology Shenzhen China

ISBN: (数字)9798350351019

ISBN: (纸本)9798350351026

Computational electromagnetics methods for analysing nonlinear systems are computationally complex, such as harmonic balance (HB) method, especially when dealing with a large number of frequency points. In this paper, we propose a fast parallel algorithm for HB method to accelerate electromagnetic simulation. the new algorithm parallelizes the construction of nonlinear Jacobian matrix, utilizing graphical processing unit (GPU) to realize improvements for electromagnetic simulation. We present the formulations of the parallel HB method, and subsequently provide its implementation details based on the mixed platform with GPU and CPU. Experimental results from several industrial cases illustrate that the new parallel algorithm leads to $3 \times$ speedup compared to the conventional HB method while still maintaining the similar accuracy, where the GPU-accelerated part is about 10 times faster than its CPU counterpart.

关键词： Jacobian matrices Accuracy Graphics processing units Harmonic analysis Computational electromagnetics Central processing Unit parallel architectures parallel algorithms Electromagnetics Nonlinear systems

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Applying K-means clustering and genetic algorithm for solving MTSP 11th

Applying K-means clustering and genetic algorithm for solvin...

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11th international conference on Bio-inspired Computing – theories and Applications, BIC-TA 2016

作者： Lu, Zhanqing Zhang, Kai He, Juanjuan Niu, Yunyun School of Computer Science Wuhan University of Science and Technology Wuhan430081 China Hubei Province Key Laboratory of Intelligent Information Processing and Real-time Industrial System Wuhan430081 China School of Information Engineering China University of Geosciences Beijing100083 China

ISBN: (纸本)9789811036132

In this paper, a new algorithm is designed to solve Multiple Traveling Salesman Problem (MTSP) that avoiding the path intersection among the traveling salesmen. there are three objectives in this problem including the shortest path of every salesman, the balance of each salesmans task and avoiding the crosses of each routes. We combine the K-means algorithm and genetic algorithm. K-means algorithm is designed to divide all points into several subsets and choose the start city for the genetic algorithm, and then using GA to process every subsets in parallel. this method not only achieve these multiple objectives, but also use much less time, since we have divided all the points into several parts and make them calculated at the same time. © Springer Nature Singapore Pte Ltd. 2016.

关键词： Genetic algorithms

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Distributed modeling and implementation of high performance communication architectures

Distributed modeling and implementation of high performance ...

引用

international conference on Distributed Computing Systems

作者： K. Shafer M. Ahuja Office of Research Online Computer Library Center Inc. Dublin OH USA Department of Comp. Science and Engineering University of California San Diego CA USA

High performance distributed computing systems require high performance communication systems. Distributed modeling and implementation of these communication systems is important. Toward this goal, the authors refine the process-to-channel/sub agent/-to-process (PCP) model of asynchronous distributed communication. While the PCP model provides a versatile and succinct mechanism for specifying and comparing different types of channels, it is inherently centralized. the refined model presented here, the process-to-channel/sub agent/-to-channel/sub agent/-to-process (PCCP) communication model, is amenable to distributed modeling and implementation of channels. the usefulness of the PCCP model is demonstrated by presenting a distributed implementation of hierarchical F-channels.< >

关键词： Distributed control Computer architecture Distributed computing High performance computing Road transportation Libraries parallel processing Message passing Algorithm design and analysis Distributed algorithms

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Stream register files with indexed access

Stream register files with indexed access

引用

IEEE Symposium on High-Performance Computer Architecture

作者： N. Jayasena M. Erez J.H. Ahn W.J. Dally Computer Systems Laboratory University of Stanford Stanford CA USA

Many current programmable architecture designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. Applications with less regular data access patterns perform sub-optimally on such architectures. We present a register file for streams (SRF) that allows arbitrary, indexed accesses. Compared to sequential SRF access, indexed access captures more temporal locality, reduces data replication in the SRF, and provides efficient support for certain types of complex access patterns. Our simulations show that indexed SRF access provides speedups of 1.03x to 4.1x and memory bandwidth reductions of up to 95% over sequential SRF access for a set of benchmarks representative of data-parallel applications with irregular accesses. Indexed SRF access also provides greater speedups than caches for a number of application classes despite significantly lower hardware costs. the area overhead of our indexed SRF implementation is 11%-22% over a sequentially accessed SRF, which corresponds to a modest 1.5%-3% increase in the total die area of a typical stream processor.

关键词： parallel processing Registers Concurrent computing Delay Computer architecture Bandwidth Application software Microprocessors Graphics Cryptography

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Design Space Exploration for a Co-designed Accelerator Supporting Homomorphic Encryption

Design Space Exploration for a Co-designed Accelerator Suppo...

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international conference on Control Systems and Computer Science (CSCS)

作者： Ghada Abozaid Ahmed El-Mahdy Parallel Computing Lab. Egypt-Japan University of Science and Technology (E-JUST) Alexandria Egypt (on-Leave) Faculty of Engineering Alexandria University Egypt

Fully Homomorphic Encryption is currently a sound theoretical approach for cloud security, it is currently not practically used due to the tremendous computation requirements of multiplying very large, million-bit, operands. In this paper, we explore the design space of software/hardware (SW/HW) co-designed accelerator relying on integrating fast software multiplication algorithms with a configurable hardware multiplier. the multiplier is based on a modified serial-parallel multiplier design, in which School-Book is a special case. the paper conducts an analytic performance study, exploring key design space parameters as well as comparing with other design approaches in the literature. Based on an actual FPGA implementation, we estimate a power consumption of 10, Watt, and area-time-power of 20.20 billion transistor-sec-Watt, potentially allowing for promising scalability.

关键词： Hardware Software Software algorithms Algorithm design and analysis parallel processing Space exploration Mathematical model

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A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

A data-flow graph generation algorithm for a coarse-grained ...

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international conference on ASIC

作者： Chao Yang Shouyi Yin Leibo Liu Shaojun Wei Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing China Tsinghua University Beijing Beijing CN

In this paper, we present a C-to-DFG generation algorithm for coarse-grained reconfigurable processor in multimedia application field. the algorithm exploits the operation parallelism available in the sequential code; maximizes parallelism by loop unrolling and scalar replacement. Loop unrolling increases the size of basic block and fully exposes the intrinsic data parallelism. Scalar replacement eliminates memory access instructions from the basic block under the prerequisite condition of keeping data dependency. For mapping kernels, the three parts of DFGs are corresponding to the three sub-components of reconfigurable unit. the experiments evaluating the degrees of parallelism on DFGs suggest 5.2x to 120.4x speedups on four kernels from common multimedia algorithms.

关键词： Hardware parallel processing Computer languages Kernel Programming profession Chaos Embedded computing High level languages Reconfigurable architectures Bridges

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