this paper proposes a novel approach to program development for highly parallelarchitectures, primarily as far as debugging is concerned. the visual nature of the debugging stage, when dealing with image-processing a...
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the Symposium materials contain 118 papers on new developments in parallelprocessing. algorithms, architectures, mapping/scheduling, applications, special-purpose architectures, interconnection networks, software, an...
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ISBN:
(纸本)0818626720
the Symposium materials contain 118 papers on new developments in parallelprocessing. algorithms, architectures, mapping/scheduling, applications, special-purpose architectures, interconnection networks, software, and distributed systems are among the main topics covered.
It has been already demonstrated that cost-effective multiprocessor designs may be obtained by combining in the same architecture processors of different speeds (heterogeneous architecture) so that the serial and crit...
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ISBN:
(纸本)0818626720
It has been already demonstrated that cost-effective multiprocessor designs may be obtained by combining in the same architecture processors of different speeds (heterogeneous architecture) so that the serial and critical portions of the application may benefit from a fast single processor. this paper presents a systematic way to build static heuristic scheduling algorithms for such environments. Several algorithms are proposed and their performance are compared through simulation. One of the proposed algorithms is shown to achieve substantial performance gains as the degree of heterogeneity of the architecture increases.
the proceedings contain 76 papers. the special focus in this conference is on parallelarchitectures and Languages Europe. the topics include: A parallel computer system for advanced information processing;a decomposi...
ISBN:
(纸本)9783540555995
the proceedings contain 76 papers. the special focus in this conference is on parallelarchitectures and Languages Europe. the topics include: A parallel computer system for advanced information processing;a decompositional approach to the design of efficient parallel programs;space-efficient parallel merging;on embedding interconnection networks into rings of processors;asynchronous mobile processes and graph rewriting;PTAH introduction to a new parallel architecture for highly numeric processing;optimal algorithms for dissemination of information in generalized communication modes;efficient parallelalgorithms on interval graphs;a SIMD computer performing the low and intermediate levels of image processing;1-dimensional parallel FFT benchmark on SUPRENUM;on designing fault-tolerant extensions with optimal fanout for complete bipartite networks;application-specific deadlock free wormhole routing on multicomputers;scalability problems in multiprocessors with private caches;promises and issues in optical computing;a model to design reusable parallel software components;extensibility and reuse of object-oriented synchronization components;using parallelism and pipeline for the optimisation of join queries;performance evaluation of parallel transaction processing in shared nothing database systems;explicit expression of multidimensional data parallelism;programming massively parallelarchitectures with sequential object oriented languages;a new program transformation to minimise communication in distributed memory architectures;distributed termination enforcement;verification of systolic architecture designs;reduction operators in alpha;an operational semantics for a parallel functional language with continuations;a concurrent and distributed extension of scheme;new techniques for cycle shrinking and loop restructuring techniques for thrashing problem.
Many elementary numerical algorithms involve not only vector operations but also matrix operations. Today's vector processors only support vector operations, and execute matrix operations in terms of vector operat...
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ISBN:
(纸本)0818626720
Many elementary numerical algorithms involve not only vector operations but also matrix operations. Today's vector processors only support vector operations, and execute matrix operations in terms of vector operations, because they can not access matrix operands in one instruction. this will lead to poor sustained performances of vector machines. In this paper we will discuss how to support both vector operations and matrix operations in vector architectures. At first subarray patterns for vector and matrix operations are introduced. then we present a set of accessing modes which can make vector architectures to access both vector and matrix operands. Finally the performance improvement for matrix multiplication and the FFT is demonstrated.
the proceedings contain 104 papers. the topics discussed include: incrementally extensible hypercube (IEH) graphs;efficient distributed routing algorithms for a synchronous circuit-switched hypercube;distributed algor...
ISBN:
(纸本)0780306058
the proceedings contain 104 papers. the topics discussed include: incrementally extensible hypercube (IEH) graphs;efficient distributed routing algorithms for a synchronous circuit-switched hypercube;distributed algorithms for shortest-path, deadlock-free routing and broadcasting in Fibonacci cubes;predicting the limits of multiple processor performance using job profiles;performance modeling of a shared-memory multiprocessor system;the performance of local and global scheduling strategies in multi-programmed parallel systems;partially shared variables and hierarchical shared memory multiprocessor architectures;and throughput enhancement in multiprocessor architectures for pipelining and digital signal processing applications.
this paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a s...
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ISBN:
(纸本)0818626720
this paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes communicating through shared memory. Several different parallelalgorithms for N-body simulation are presented in Proteus, illustrating how Proteus provides a common foundation for expressing the various parallel programming models. this common foundation allows prototype parallel programs to be tested and evolved without the use of machine-specific languages. To transform prototypes to implementations on specific architectures, program refinement techniques are utilized. Refinement strategies are illustrated that target broad-spectrum parallel intermediate languages, and their viability is demonstrated by refining an N-body algorithm to data-parallel CVL code.
Window-based parallelarchitectures are considered as target structures for the computation of low and medium level image processingalgorithms. their definition stems from a general reformulation of algorithms, based...
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Window-based parallelarchitectures are considered as target structures for the computation of low and medium level image processingalgorithms. their definition stems from a general reformulation of algorithms, based on local data processing. A methodology for high level global evaluation of such architectures is presented, considering the reachable performances of the structures as main significant parameters.< >
An event-driven simulator for performance evaluation and modeling of parallelprocessing systems and parallelalgorithms is presented. the system topology and architectural details are input to the simulator by means ...
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Rank order filters form an important class of low level image operations that have widespread applications in image smoothing, texture analysis, etc. In this paper, we study several ways of computing rank order filter...
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