the Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. the system can achieve 20 Giga-flops ...
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the Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. the system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. the system employs a hierarchical reconfigurable interconnection network withthe highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. the system is designed to use 256 to 1024 RISC processors. the processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. the system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance.< >
the authors are concerned with performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures operating in real-time. the mapping of real-time algorithm...
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ISBN:
(纸本)0818621338
the authors are concerned with performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures operating in real-time. the mapping of real-time algorithms onto data flow architectures is realized by a marked graph model called ATAMM (algorithm to architecture mapping model). Applications include control, surveillance, and signal processing problems. Performance is characterized by computing speed and throughput. Bounds on performance measures are established. A technique for transforming an algorithm to improve throughput while maintaining input-output equivalence is presented. the state equations of a linear time invariant system are modified to illustrate the throughput enhancement technique.
this conference proceedings consists of 121 papers. the following topics are dealt with: real time architectures and applications;neural network implementation and applications;parallelism and computational paradigms ...
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ISBN:
(纸本)0818621338
this conference proceedings consists of 121 papers. the following topics are dealt with: real time architectures and applications;neural network implementation and applications;parallelism and computational paradigms of the future;fault tolerance and reliability;performance measurement and evaluation;distributed database systems;parallel and distributed architectures;parallel and distributed algorithms and applications;distributed operating systems;algorithms for distributed operating systems;languages and environments;object-oriented systems;specification methodologies;software engineering;communications theory;recent advances in mobile digital radio;advanced topics in communications systems;digital communications;theory and applications of non-uniform sampling;fiber optics;frame relay networks;network management and standards;protocol design;network performance;local area networks;wide area and broadband networks;multimedia database systems;graphics and multimedia;computer aided design;deductive systems;expert system applications;and AI techniques and expert systems.
It is shown how a parallel object model can be used as a support environment for massively parallelarchitectures based on transputer technology. the intention is to verify that parallelism integrates well with such p...
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ISBN:
(纸本)0818621338
It is shown how a parallel object model can be used as a support environment for massively parallelarchitectures based on transputer technology. the intention is to verify that parallelism integrates well with such properties of the object paradigm as abstraction, uniformity, and dynamicity. the authors also present the guidelines to build prototypes by an approach based on primitives. In particular, the implemented primitives make possible the creation and communication of objects for a massively parallel architecture. Finally, trends in future work--static and dynamic allocation, replication and persistency of objects--are outlined.
the authors describe the use of an associative image classification architecture to estimate the camera-driven position of a land vehicle. Outdoor pictorial scenes are used within a vision system for the positioning o...
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ISBN:
(纸本)0818621338
the authors describe the use of an associative image classification architecture to estimate the camera-driven position of a land vehicle. Outdoor pictorial scenes are used within a vision system for the positioning of an autonomous land vehicle. Images supplied by sensorial input sources are matched with a set of simplified descriptions of possible scenes (prototypes). the associative classification module must supply a rough suggestion about the observed scene to a top-down expectation-driven recognition system. Easy training, low computation times, and ordering alternatives according to their evaluated reliabilities are some of the most important advantages of the approach described. Experimental results show that the classification mechanism operates correctly also in the presence of very similar training patterns. the system's structural flexibility allows efficient application-oriented implementations on low-cost parallel machinery.
this paper presents the concepts, architecture, and features of a tool for instrumenting parallel and distributed systems. this capability will be useful in evaluating alternative architectures and strategies for dist...
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this paper presents the concepts, architecture, and features of a tool for instrumenting parallel and distributed systems. this capability will be useful in evaluating alternative architectures and strategies for distributing application software, detecting performance bottlenecks, quantifying and fine-tuning real-time performance, detecting and isolating behavior anomalies, and characterizing the behavior of specific algorithms under desired stimulation conditions. the Honeywell instrumentation system provides a flexible capability for selecting and customizing existing instrumentation functions, synthesizing new instrumentation functions, and tailoring/scaling instrumentation to a particular architecture or application domain.
Structure-oriented computer architecture is a research direction that tries to join the parallelprocessing facilities and decentralized control of multiprocessors or data-flow architectures withthe efficient memory ...
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ISBN:
(纸本)081862048X
Structure-oriented computer architecture is a research direction that tries to join the parallelprocessing facilities and decentralized control of multiprocessors or data-flow architectures withthe efficient memory access and pipelining techniques of data structure architectures. the main concepts and the motivation for introducing this term are shown. Data structure architectures are compared withthe successful concept of multiprocessors, and some limits of the latter are shown. the term 'structure-oriented computer architectures' is introduced for a class of compound architectures built up from two rival architecture classes. Some effects of these architectures on software quality are discussed. An example of a proposed structure-oriented computer architecture is presented.
this volume contains 121 papers. the topics dealt with include: focus of attention;neural networks in image and speech processing;digital signal processing;coding;parallelarchitectures;VLSI architectures;software too...
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this volume contains 121 papers. the topics dealt with include: focus of attention;neural networks in image and speech processing;digital signal processing;coding;parallelarchitectures;VLSI architectures;software tools for image understanding;and next-generation architectures integrating sensory and symbolic processing.
A system for dynamic intelligent scheduling and control (DISC) of reconfigurable parallel processors is presented. the purpose of the system is to provide a rapid prototyping capability for computer vision/image proce...
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A system for dynamic intelligent scheduling and control (DISC) of reconfigurable parallel processors is presented. the purpose of the system is to provide a rapid prototyping capability for computer vision/image processing tasks. the scheduler particularly addresses the problems of algorithms with execution times that depend on the image data and processing scenarios that vary dynamically based on the input image. Since conventional scheduling methods cannot propose schedules for most masks of this type, a dynamic controller is used to schedule the task and reconfigure the machine on the fly. this dynamic scheduling system attempts to balance the overall processing scenario withthe needs of the individual routines that make up the task. the implementation of this system is discussed, with emphasis on the scheduling heuristics and the use of the system for prototyping computer vision/image processing tasks. Testing was done on a number of tasks that exercised different aspects of the scheduling strategy. the schedules determined by DISC have an average tiling percentage of 77% and an average scheduling overhead of only 0.1% of the total task execution time.
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