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HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTION REACTION

HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTIO...

10th IUPAC international conference on Novel Materials and their Synthesis NMS-X(IUPAC第十届新材料及其合成国际会议)

作者： Daping He Peng Wu Xu Chen Hui Wu Shichun Mu State Key Laboratory of Advanced Technology for Materials Synthesis and Processing Wuhan University of TechnologyWuhan 430070P.R.China

Hitherto, the low electrochemical stability of the catalyst is one of the big issues hindering the commercial application of proton exchange membrane fuel cells (PEMFCs) . In this work, more stable support materials based on functionalized graphene nanosheets (GNS), porous GNS, heteroatom doped GNS, and alternative GNS composites including GNS/nano-carbon (or nano-ceramics) sandwiches, nanoceramic wedged GNS, and core-shell graphene and amorphous carbon composites are prepared and applied in catalysts towards oxygen reduction reaction (ORR). based on the idea of bifunction of GNS to Pt catalysts, highly active and stable Pt/reduced graphene oxide (RGO) catalysts are developed by tuning the O/C atom ratio of RGO supports where the optimized O/C atom ratio of 0.14 is determined. Meantime, both perfluorosulfonic acid (PFSA) functionalized GNS and sulfonic acid group-grafted RGO supported Pt catalysts show a higher catalytic activity and a lower loss rate of electrochemical active area (ECA) in comparison with that of the plain Pt/GNS and conventional Pt/C catalysts. In addition, the N-doped RGO supported Pt catalyst (Pt/NRGO) is synthesized using a lyophilisation-assisted N-doping method, revealing a higher catalytic activity and a lower ECA loss of the Pt/NRGO catalyst to compare with that of the Pt/GO and Pt/C catalysts. In addition, to tackle the stacking issues of GNS which leads to the low mass transport property, the porous GNS are synthesized. Besides, we also describe a new strategy to synthesize GNS hybrids including GNS/nano-carbon (nano-creamics) sandwiches and nano-ceramic wedged GNS architectures. these unique architectures with highly dispersed Pt NPs exhibit much high catalytic activities towards ORR and an excellent electrochemical stability. At last, a new graphene @ amorphous carbon core-shell material also shows an excellent electrochemical property. this work was supported financially by the National Natural Science Foundation of China (NSFC) (No. 5

关键词： catalysts graphene oxygen reduction fuel cells

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Single Operation Multiple Data - Data parallelism at Subroutine Level

Single Operation Multiple Data - Data Parallelism at Subrout...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Eduardo Marques Hervé Paulino CITI / Departamento de Informática Faculdade de Ciências e Tecnologia Universidade Nova de Lisboa Caparica Portugal

the parallel nature of the multi-core architectural design can only be fully exploited by concurrent applications. this status quo pushed productivity to the forefront of the language design concerns. the community is demanding for new solutions in the design, compilation, and implementation of concurrent languages, making this research area one of great importance and impact. To that extent this paper proposes the expression of data parallelism at subroutine level. the calling of a subroutine in this context spawns several execution flows, each operating on distinct partitions of the input dataset. Such computations can be expressed by simply annotating sequential subroutines with data distribution and reduction policies, delegating the management of the parallel execution to a dedicated runtime system. the paper overviews the key concepts of the model, illustrating them with some small programming examples, and describes a Java implementation built on top of the X10 [1] runtime system. A performance evaluation attests that this approach can provide good performance gains without burdening the programmer with the writing of specialized code.

关键词： Arrays Java Runtime Synchronization algorithms Computational modeling parallel processing

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An Efficient, QoS-Aware I/O Scheduler for Solid State Drive

An Efficient, QoS-Aware I/O Scheduler for Solid State Drive

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Quan Zhang Dan Feng Fang Wang Yanwen Xie Wuhan National Laboratory for Optoelectronic Huazhong University of Science & Technology Wuhan China

Flash-based solid-state drive has been proved to be a competitive alternative to mechanical disk for its high performance and low power consumption. But SSD still suffers from relatively high price and low density, which calls for consolidating device resource to bring down the cost of deploying expensive dedicated flash-based storage systems for specific applications. Within such environment, applications may compete for storage service and interfere with each other. therefore, storage service providers must ensure performance isolation. However, current research mainly focuses on performance guarantees on mechanical disk. In this paper, we present a 2-level scheduling framework where the higher level targets performance isolation through distinguishing the cost of read and write operations in SSD, and the lower level builds channel-based queues for SSD to exploit the inherent parallelism of SSD. Synthetic and real workloads are used in our evaluation to demonstrate the effectiveness of our 2-level scheduling framework, and the results show it outperforms other I/O schedulers at both aspects of performance isolation and I/O efficiency.

关键词： Performance evaluation Quality of service parallel processing Ash Resource management throughput Equations

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Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler 07

Improving Performance Isolation on Chip Multiprocessors via ...

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international conference on parallel Architecture and Compilation Techniques (PACT)

作者： Alexandra Fedorova Margo Seltzer Michael D. Smith Simon Fraser University Harvard University

ISBN: (纸本)9780769529448

We describe a new operating system scheduling algorithm that improves performance isolation on chip multiprocessors (CMP). Poor performance isolation occurs when an application's performance is determined by the behaviour of its co-runners, i.e., other applications simultaneously running with it. this performance dependency is caused by unfair, co- runner-dependent cache allocation on CMPs. Poor performance isolation interferes with the operating system 's control over priority enforcement and hinders QoS provisioning. Previous solutions required modifications to the hardware. We present a new software solution. Our cache-fair algorithm ensures that the application runs as quickly as it would under fair cache allocation, regardless of how the cache is actually allocated. If the thread executes fewer instructions per cycle than it would under fair cache allocation, the scheduler increases that thread's CPU time slice. this way, the thread's overall performance does not suffer because it is allowed to use the CPU longer. We describe our implementation of the algorithm in Solaristrade 10, and show that it significantly improves performance isolation for SPEC CPU, SPEC JBB and TPC-C.

关键词： System-on-a-chip Operating systems Yarn Hardware Scheduling algorithm Application software Control systems Processor scheduling Partitioning algorithms parallel architectures

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Using a multitasking GPU environment for content-based similarity measures of big data

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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2013年 7971卷 181-196页

作者： Tarakji, Ayman Hassani, Marwan Lankes, Stefan Seidl, thomas RWTH Aachen University Aachen Germany Data Management and Data Exploration Group RWTH Aachen University Germany

ISBN: (纸本)9783642396366

Performance and efficiency became recently key requirements of computer architectures. Modern computers incorporate Graphics processing Units (GPUs) into running data mining algorithms, as well as other general purpose computations. In this paper, different parallelization methods are analyzed and compared in order to understand their applicability. From multi-threading on shared memory to using NVIDIA's GPU accelerators for increasing performance and efficiency on parallel computing, this work discusses the parallelization of data mining algorithms considering performance and efficiency issues. the performance is compared on both many-core systems and GPU accelerators on a distance measure algorithm using a relatively big data set. We optimize the way we deal with GPUs in heterogeneous systems to make them more suitable for big data mining applications with heavy distance calculations. Moreover, we focus on achieving a higher utilization of GPU resources and a better reuse of data. Our implementation of the content-based similarity algorithm SQFD on the GPU outperforms by up to 50 x CPU counterparts, and up to 15x CPU multi-threaded implementations. © Springer-Verlag Berlin Heidelberg 2013.

关键词： Graphics processing unit

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parallel multiple precision division by a single precision divisor

Parallel multiple precision division by a single precision d...

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international conference on High Performance Computing

作者： Niall Emmart Charles Weems Computer Science Department University of Massachusetts Amherst MA USA

We report an algorithm for division of a multi- precision integer by a single-precision value using a graphics processing unit (GPU). Our algorithm combines a parallel version of Jebelean's exact division algorithm with a left-to- right algorithm for computing the borrow chain, to relax the requirement of exactness. We also employ Takahashi's recently reported cyclic reduction technique [10] for GPU division to further enhance performance. the result is that our algorithm is asymptotically faster, at O(n/p + log p), than Takahashi's algorithm at 0(n/p log p). We report results for dividends with precisions of 1024, 2048, and 4096 bits running on an NVIDIA GTX 480, and show that, for non-constant divisors, our algorithm is 20% slower at 1024 bits (due to startup overhead), by 2048 we are 40% faster, and at 4096 bits we are able to run 2.5 times faster. For division by constants, with precomputed tables, our algorithm is faster at all sizes with a speedup ranging from 2.3 to 6 times faster.

关键词： parallel algorithms Algorithm design and analysis Context Graphics processing unit Educational institutions Indexes Cognition

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Implementation with FPGAs of a pipelined on-line backpropagation

Implementation with FPGAs of a pipelined on-line backpropaga...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： R.G. Girones A.M. Salcedo Departmento Ing. Electrónica UPV Valencia Spain

the paper describes the implementation of a systolic array for a multilayer perceptron on ALTERA FLEX10KE FPGAs with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. As a result, a combined systolic array structure is proposed for both phases. Analytic expressions show that the pipelined version is more efficient than the non-pipelined version. the design is implemented and simulated using VHDL at different levels of abstraction and finally mapped on FPGAs.

关键词： Field programmable gate arrays Artificial neural networks parallel processing Backpropagation algorithms Signal processing algorithms Neurons Hardware Systolic arrays Multilayer perceptrons Neural networks

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A Feature Selection Method of parallel Grey Wolf Optimization Algorithm Based on Spark

A Feature Selection Method of Parallel Grey Wolf Optimizatio...

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IEEE international Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications

作者： Hongwei Chen Lin Han Zhou Hu Qiao Hou Zhiwei Ye Jun Zeng Jiansen Yuan School of Computer Science Hubei University of Technology Wuhan China Wuhan Fiberhome Technical Services Co. Ltd. Wuhan

Feature selection is a technique for selecting a set of related features that contribute the most to the accuracy of the classifier from the feature set. Feature selection has always been an active research field in the past ten to fifteen years. Due to a large amount of data and the high computational complexity caused by the high dimensionality of data, the single-machine processing time is too long. To address this shortcoming, this paper proposes a Spark-based platform. the feature selection method of the parallel binary gray wolf optimization algorithm (SPBGWO) has higher search performance, which can improve the shortcomings of the algorithm which is easy to fall into local optimum and improve the convergence efficiency of the algorithm. Combining the improved search capabilities of the improved gray wolf algorithm with the computing power of the Spark platform simplifies the high complexity of large data volumes and computations, making the algorithm simpler, faster, better able to solve problems and reduce storage requirements.

关键词： Xenon

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Enhancing Tamil Handwritten Character Recognition Using Multimodel Deep Learning

Enhancing Tamil Handwritten Character Recognition Using Mult...

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international conference on Communications and Signal processing

作者： R. thendral M. Subasri G. Sudharsan M.K. Ragul Department of Information Technology IFET College of Engineering Villupuram Tamilnadu

ISBN: (数字)9798350353068

ISBN: (纸本)9798350353075

Based of the intricate script and lengthy history of the language, handwritten character identification in Tamil presents particular difficulties. In order to improve the accuracy of Tamil handwritten character identification, this research suggests a unique method that makes use of multimodel deep learning techniques. In response to the shortcomings of the current datasets, we provide the unconstrained Tamil Handwritten Character Database (uthCD) dataset. RESNET50, VGG16, and LeNet50 architectures are used in our methods to extract features and classify them. We establish the effectiveness of our method by conducting a large-scale experiment and attaining notable gains in recognition accuracy. Our results highlight the value of multimodel learning for handwritten Tamil documents preservation and digitization, enabling their smooth incorporation into digital settings.

关键词： Deep learning Handwriting recognition Databases Signal processing Feature extraction Information retrieval Character recognition

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Improving VLIW Processor Performance using three-Dimensional (3D) DRAM Stacking

Improving VLIW Processor Performance using Three-Dimensional...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Yangyang Pan Tong Zhang ECSE Department Rensselaer Polytechnic Institute

ISBN: (纸本)9781424445523

this work studies the potential of using emerging 3D integration to improve embedded VLIW computing system. We focus on the 3D integration of one VLIW processor die with multiple high-capacity DRAM dies. Our proposed memory architecture employs 3D stacking technology to bond one die containing several processing clusters to multiple DRAM dies for a primary memory. the 3D technology also enables wide low-latency buses between clusters and memory and enable the latency of 3D DRAM L2 cache comparable to 2D SRAM L2 cache. these enable it to replace the 2D SRAM L2 cache with 3D DRAM L2 cache. the die area for 2D SRAM L2 cache can be re-allocated to additional clusters that can improve the performance of the system. From the simulation results, we find 3D stacking DRAM main memory can improve the system performance by 10%～80% than 2D off-chip DRAM main memory depending on different benchmarks. Also, for a similar logic die area, a four clusters system with 3D DRAM L2 cache and 3D DRAM main memory outperforms a two clusters system with 2D SRAM L2 cache and 3D DRAM main memory by about 10%.

关键词： VLIW Random access memory Stacking Digital signal processing Embedded computing parallel processing Computer architecture USA Councils Delay System performance

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