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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Archite...

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Proceedings of the 13th international conference on Distributed Smart Cameras

作者： Walther Carballo-Hernández François Berry Maxime Pelcat Miguel Arias-Estrada Department of Images Perception Systems and Robotics Institut Pascal Aubière France Department of Images Institut National des Sciences Appliquées (INSA) des Rennes IETR UMR CNRS Rennes France Department of Computer Science Instituto Nacional de Astrofísica (Óptica y Electrónica (INAOE) Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia® Jetson TX2 for the CPU-GPU side and an Intel Altera® Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Internet of things Field Programmable Gate Array (FPGA) Graphic processing Unit (GPU) Deep Learning (DL) Edge Computing processing Elements (PE) Artificial Neural Networks (ANN) Single Instruction Multiple Data Convolutional Neural Networks (CNN) Models of Computation and Architecture Pipelining Heterogeneous Computing parallel Programming

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A fully digital Background calibration technique for pipeline analog-to-digital converters

A fully digital Background calibration technique for pipelin...

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international conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON

作者： Ziaeddin Koozeh Kanani Jafar Sobhi Mousa Yousefi Ahmad Tahmasebi Department of Electrical Engineering University of Tabriz Tabriz Iran Sarab Branch Islamic Azad University Sarab Iran

this paper describes a new background calibration technique for pipeline analog-to-digital converters (ADCs). the new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. the goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. the extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. the digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12 bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.

关键词： Calibration Pipelines Analog-digital conversion Voltage Operational amplifiers Topology Signal processing algorithms Capacitors Signal resolution Aging

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Data processing Unit (DPU) Based Network Process Offloading for Efficient Service Meshes

Data Processing Unit (DPU) Based Network Process Offloading ...

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IEEE conference on Network Softwarization (NetSoft)

作者： Karumuri Meher Hasanth Shoaib Basu Deepak Nadig Dept. of Computer and Information Technology Purdue University West Lafayette IN

ISBN: (数字)9798350369588

ISBN: (纸本)9798350369595

As the software development landscape transitions from monolithic applications to agile, cloud-native microservices, new challenges in communication have emerged, necessitating the evolution of network service meshes to effectively manage these complexities. While addressing these communication challenges, implementing service mesh solutions introduces higher resource utilization, primarily due to deploying an additional per-microservice infrastructure known as the “sidecar” container. A sidecarless approach, as exemplified by Cilium, leverages extended Berkeley packet filter (eBPF) technology to minimize operational overhead and optimize resource utilization. the advent of data processing units (DPU) represents a crucial evolution in cloud accelerators, designed to offload and accelerate networking, security, and storage tasks traditionally handled by server CPUs. this demonstration integrates DPU technology with Cilium’s sidecarless architecture and proposes to offload Cilium’s control plane to DPUs. Our proposed approach improves system efficiency by deploying Cilium’s control plane components on DPUs in a separate host mode. Further, our approach conserves CPU cycles on the primary hosts and shifts network processing tasks to the DPU. this strategic offload aims to enhance throughput, reduce latency, and unburden CPUs from network processing tasks to improve the performance of service mesh architectures for cloud-native ecosystems.

关键词： Microservice architectures Computer architecture Data processing throughput Resource management Servers Security

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Real-time wideband DDC based on parallel architecturein synthetic instrument

Real-time wideband DDC based on parallel architecturein synt...

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Measurement Touch the World——IEEE 2011 10th international conference on Electronic Measurement & Instruments(ICEMI’2011)

作者： Guo Lianping Tian Shulin Wang Zhigang School of Automation Engineering University of Electronic and Science Technology of China Chengdu 610054 China

Restricted by the processing speed of device,bandwidth and filter performance of Wideband Digital IF Process are hard to achieve a *** this paper,to solving the problems during wideband digital IF process,a parallel processing architecture is presented to efficiently lower the sample rate and process cost through multiple channels of parallel *** paper deduces the digital down conversion technique principle,analyzes output phase difference of multiple Numerical Control Oscillator’s（NCO） output and error factor for reducing SNR,and provides the index distribution basis for the specific engineering ***,the correctness is verified by the experimental platform.

关键词： wideband digital IF process DDC phase difference quantization effects synthetic instruments

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Adding limited reconfigurability to superscalar processors 04

Adding limited reconfigurability to superscalar processors

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international conference on parallel Architecture and Compilation Techniques (PACT)

作者： M. Epalza P. Ienne D. Mlynek Signal Processing Institute Switzerland Processor Architecture Laboratory Switzerland Swiss Federal Institute of Technology Lausanne Switzerland

ISBN: (纸本)9780769522296

When adding reconfigurability to custom hardware, one must take great care that the reduction in speed due to the reconfigurable logic should not cancel out the gains obtained by reconfiguration. these gains are greatest in very specific and computation-intensive applications, and lessen as the applications become more general and heterogeneous. In the case of superscalar processors, this leads to limiting the amount of reconfigurability to precise changes in existing functional units instead of adding a fully configurable functional unit. We present a detailed study of the modifications necessary in a superscalar processor to allow an FPU to be dynamically reconfigured as several ALUs with a minimal increase in the latency of these functional units. the timing of the FPU's multiplier tree and the decision about reconfiguration are exposed. As there is more than one simple unit involved, this decision is more global than a cycle-by-cycle reconfiguration and must be made for a longer period of time. We discuss possible policies for the dynamic reconfiguration decisions. the results show interesting gains of up to 56% in the best cases, and average gains of 10%, on typical architectures over a wide range of applications.

关键词： Reconfigurable logic Field programmable gate arrays Hardware Signal processing Delay Automatic control Switches Computer applications Limiting Timing

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Constant-Weight Group Coded Bloom Filter for Multiple-Set Membership Queries 10th

Constant-Weight Group Coded Bloom Filter for Multiple-Set Me...

引用

10th international conference on Computer Engineering and Networks, CENet 2020

作者： Tian, Xiaomei Zhao, Huihuang College of Computer Science and Technology Hengyang Normal University Hengyang421002 China Hunan Provincial Key Laboratory of Intelligent Information Processing and Application Hengyang421002 China

ISBN: (纸本)9789811584619

Multiple-set membership query problem plays a very important role in many network systems, including packet forwarding architectures in big data centers, routing switching devices and internet firewall systems. Many solutions to multiple-set membership query problem are based on Bloom filters. And each of these solutions has its own merits. Some have high query speed and some have good accuracy. But generally, they cannot have both at the same time. In this paper, we propose a probabilistic data structure named constant-weight group coded Bloom Filter (CWGCBF) for fast and accurate multi-set membership query. the key technique in CWGCBF is encoding each elements set ID to constant weight code, and directly recording this constant-weight code in the bloom filter vector. Experimental results show that in terms of false positive ratio, CWGCBF, Shifting Bloom Filter and Combinatorial Bloom Filter have great advantages to the other compared Bloom filters, and in terms of time efficiency, CWGCBF and ID Bloom Filter are several times faster than the others. © 2021, the Editor(s) (if applicable) and the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Data structures

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Enhancing the Performance of an Image Steganalysis Approach Using Variable Batch Size-Based CNN on GPUs

Enhancing the Performance of an Image Steganalysis Approach ...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Eslam M. Mustafa Mohamed M. Fouad Mohamed A. Elshafey Military Technical College Cairo Egypt

Blind image steganalysis is defined as the binary classification problem of predicting whether or not an image contains an embedded message. With the development of steganography, extracting powerful features from the stego-images becomes a challenge. Recently, convolutional Neural Networks (CNNs) are presented as a promising solution for such a challenge. Unlike traditional steganalysis approaches, CNN-based steganalysis approaches have the ability of extracting features automatically from input images. With such an ability, there is no need to handcraft feature extractors like those used by traditional steganalysis approaches. Despite its long clinical success, CNN-based steganalysis approaches are time consuming. Training on those approaches may stand for days and sometimes for weeks. It is necessary to accelerate the training on CNN-based approaches to make them more usable in practice, especially for some real-time applications. the purpose of this paper is to implement an enhanced version of the improved Gaussian-Neuron CNN (IGNCNN) steganalysis approach on GPUs, and to profiteer the parallel power of GPUS. In this paper two approaches for parallelizing the CNN training process are proposed. the first is to apply the concept of data parallelism with the feature extraction module and the second is to apply model parallelism with the classification module. Besides the parallelization approaches, a variable batch size is implemented as an optimization approach. Using a big batch size in fully-connected layers leads to faster convergence to a better minima, but it may negatively affect the accuracy. the results of the proposed approach show that it outperforms the IGNCNN in terms of accuracy and performance metrics.

关键词： parallel processing Training Data models Graphics processing units Feature extraction Computational modeling Acceleration

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Enhancing Web Service Composition Security with Formal Methods

Enhancing Web Service Composition Security with Formal Metho...

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international conference on Computer and Communications (ICCC)

作者： Li Bao School of Data Science and Application Inner Mongolia University of Technology Huhhot China

ISBN: (数字)9798331507077

ISBN: (纸本)9798331507084

this paper presents a novel approach to enhance Web service composition through the Web Service Interaction Model (IWSN). the IWSN aims to ensure accurate interaction between Web services, improve composition scalability, resolve behavioral compatibility issues during interaction, and facilitate broader adoption of service composition technologies. Based on the Kahn Process Network (KPN) for its foundation in parallel computing via data streams and channels, the proposed model establishes formal semantics using Calculus of Communication Systems. the model's properties are explored, and its application is illustrated through a case study that demonstrates its effectiveness in web service composition and interaction.

关键词： Web services Communication systems Computational modeling Scalability Semantics parallel processing Data models Calculus Computer security Streams

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Re-structuring CNN using quantum layer executed on FPGA hardware for classifying 2-D data

Re-structuring CNN using quantum layer executed on FPGA hard...

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international conference on Integrated Circuits, Design, and Verification (ICDV)

作者： Nhat Hoang Bach Le Ha Vu Dinh Lam Tran thanh Toan Dao thi thu Hong Luu Duy Ninh Nguyen Institute of Electronics Academy of Science and Technology Hanoi Vietnam Electronic department University of Transport and Communications Hanoi Vietnam

ISBN: (数字)9798350371864

ISBN: (纸本)9798350371871

the article proposes a solution to restructure Convolutional Neural Network (CNN) architectures by integrating parameter quantization techniques with traditional CNN models capable of deployment on Field-Programmable Gate Array (FPGA) hardware for evaluating the classification performance of two-dimensional data in real-world scenarios. the solution introduces an additional quantum layer before the final classification layer of the CNN to receive standardized outputs, followed by computations in the Hilbert vector space to generate probability values for assessing classification results. the quantization process helps the model swiftly identify data features while optimizing the parallel computing capability of FPGA hardware. the model is evaluated on the MNIST handwritten digit dataset, revealing two advantages: time-processing on FPGA is four times faster compared to using only the Central processing Unit (CPU) on the PynQ-z2 kit board; classification accuracy is higher when utilizing the quantum layer compared to without it, with the same number of training iterations. these results demonstrate the feasibility of hardware-accelerated AI algorithms combined with quantum algorithms in real applications.

关键词： Quantization (signal) Computational modeling Hardware Data models Vectors Central processing Unit Convolutional neural networks

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Adaptive steering of cyber-physical systems with atomic complex event processing services: doctoral symposium 16

Adaptive steering of cyber-physical systems with atomic comp...

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Proceedings of the 10th ACM international conference on Distributed and Event-based Systems

作者： Julius Ollesch University of Duisburg-Essen Essen Germany

ISBN: (纸本)9781450340212

Given the advent of cyber-physical systems (CPS), event-based control paradigms such as complex event processing (CEP) are vital enablers for adaptive analytical control mechanisms. CPS are becoming a high-profile research topic as they are key to disruptive digital innovations such as autonomous driving, industrial internet, smart grid and ambient assisted living. However, organizational and technological scalability of today's CEP approaches is limited by their monolithic architectures. this leads to the research idea for atomic CEP entities and the hypothesis that a network of small event-based control services is better suited for CPS development and operation than current centralised approaches. In addition, the paper summarizes preliminary results of the presented doctoral work and outlines questions for future research as well as an evaluation plan.

关键词： internet of things architecture microservices web services spatio-temporal processing complex event processing real-time analytics cyber-physical systems sensor networks

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