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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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A tool for real time analysis of parallelism of distribution networks

A tool for real time analysis of parallelism of distribution...

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IEEE/IAS international conference on Industry Applications (INDUSCON)

作者： L. L. Pfitscher D. P. Bernardon L. N. Canha V. F. Montagner M. Sperandio J. A. Saldanha M. S. Ramos Federal University of Santa Maria Alegrete Rio Grande do Sul Brazil Federal University of Pampa Alegrete Rio Grande do Sul Brazil AES Sul Power Utility Alegrete Rio Grande do Sul Brazil

ISBN: (纸本)9781467324120

the parallelism of distribution networks can be used to transfer loads between feeders without the need of disconnection of consumers during the switching. In the context of the Smart Grids, the parallelism of feeders can be used in automatic reconfiguration of networks for the improvement of power quality and voltage levels, and reduction of energy losses. However, the switching for parallelism must be preceded by studies to verify their technical and operational feasibility. this paper presents a study that discusses aspects of loading, protection, and voltage levels related to parallelism of networks, in transient and steady-state analysis. the validation of the developed methodology was carried out by comparison of simulation results with the ATP program. the study aims to be suitable for real-time application in reconfiguration of distribution networks. Integration with remote controlled switches, so that the network reconfiguration can be done automatically, is one of the differentials of the work. the tests here presented are made in a real model of a distribution network of a power utility. the developed algorithm has as main result a reliable indication of the technical feasibility of connecting feeders in parallel.

关键词： parallel processing Switches Load modeling Transient analysis Mathematical model Real-time systems Steady-state

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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Dynamic Occupant Adaptive Energy Management System(DOAEM) for Smart Building

Dynamic Occupant Adaptive Energy Management System(DOAEM) fo...

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IEEE international conference on Smart Instrumentation, Measurement and Applications (ICSIMA)

作者： Ghulam Fizza Kushsairy Kadir Haidawati Nasir Asadullah Shah Department of Electrical and Electronic Engineering Universiti Kuala Lumpur British Malaysian Institute (UniKL BMI) Selangor Malaysia Department of Computer Engineering Universiti Kuala Lumpur Malaysian Institute of Information Technology(UniKL MIIT) Kuala Lumpur Malaysia Department of Information Systems Kulliyyah of ICT International Islamic University Malaysia (IIUM) Kuala Lumpur Malaysia

ISBN: (数字)9798350365283

ISBN: (纸本)9798350365290

the increasing global energy demands highlight the need for improved energy management systems in smart buildings. Traditional systems are inadequate in resolving the dynamic interplay between energy consumption and occupant comfort due to their inability to adapt to the dynamic nature of occupancy. the main goal of this research is to use dynamic occupancy data to optimize energy consumption. this research introduces a solution that is African Vulture Optimization Algorithm (AVOA) based Dynamic Occupant Adaptive Energy Management System. the adoption of AVOA resulted in a significant reduction in energy consumption, with a median consumption drop of 329.39 kWhr from a baseline of non-optimized 938.08 kWhr. More specifically, the implementation of AVOA showed an average improvement in energy gain to 0.9940, demonstrating the effectiveness of the system in improving energy efficiency while maintaining occupant comfort. this research proposes an integrated approach that balances energy efficiency with the well-being of its occupants, so contributing to the broader targets of sustainable urban development

关键词： Energy consumption Smart buildings Adaptive systems Heuristic algorithms Scalability Energy conservation parallel processing

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Proteus: a reconfigurable computational network for computer vision

Proteus: a reconfigurable computational network for computer...

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international conference on Pattern Recognition

作者： R.M. Haralick A.K. Somani C. Wittenbrink R. Johnson K. Cooper L.G. Shapiro I.T. Phillips J.-N. Hwang W. Cheung Y.H. Yao C.H. Chen L. Yang B. Daugherty B. Lorbeski K. Loving T. Miller L. Parkins S. Soos Department of Electrical Engineering FT-10 Applied Physics Laboratory HN-10 University of Washington Seattle WA USA

the Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. the system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. the system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. the system is designed to use 256 to 1024 RISC processors. the processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. the system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance.< >

关键词： Computer vision Computer networks Multiprocessor interconnection networks Computer architecture Machine vision Image processing Switching circuits Hypercubes Reduced instruction set computing Electrical fault detection

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FPGA-based accelerator design from a domain-specific language

FPGA-based accelerator design from a domain-specific languag...

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international conference on Field Programmable Logic and Applications

作者： M. Akif Özkan Oliver Reiche Frank Hannig Jürgen Teich Friedrich-Alexander University of Erlangen-Ntirnberg (FAU) Germany

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： Kernel Hardware Computer architecture Programming Field programmable gate arrays Image processing

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VLSI Implementation of Level Shifter: A Review Paper

VLSI Implementation of Level Shifter: A Review Paper

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international conference on Advanced Computing and Communication Systems (ICACCS)

作者： Sreenidhi Prabha Rajeev Adithya R Baby Sreeja S D Nandu Krishnan Gowri Ganesh A Niranjan Department of Electronics and Communication Engineering Amrita Vishwa Vidyapeetham Amritapuri India

ISBN: (数字)9798350384369

ISBN: (纸本)9798350384376

Level shifters (LS) are fundamental components in modern integrated circuits, facilitating voltage translation between different domains in mixed-signal and low-power designs. this review paper presents a comprehensive analysis of Very Large-Scale Integration (VLSI) implementations of level shifters, focusing on design techniques, architectures, and performance metrics. the significance of level shifters in both analog and digital systems is discussed, emphasizing their role in ensuring compatibility and efficient signal processing. Furthermore, the continuous development of LS designs is explored in addressing challenges associated with scaling down technology nodes, enhancing energy efficiency, reducing leakage currents, and improving speed and reliability. the review also highlights the impact of LS circuits on overall system performance and efficiency. In conclusion, this paper provides valuable insights into the design and application of level shifters in modern electronic systems, paving the way for future advancements in the field.

关键词： Technological innovation Reviews System performance Very large scale integration Signal processing Reliability engineering threshold voltage Circuit synthesis Sustainable development Switching circuits

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Accelerating Transformer architectures for Automatic Modulation Classification via Gated Activation Patch Selection

Accelerating Transformer Architectures for Automatic Modulat...

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international conference on Computer and Communications (ICCC)

作者： Xitong Pu Chunbo Luo Yihao Yin Yang Luo School of Information and Communication Engineering University of Electronic Science and Technology of China Chengdu China

ISBN: (数字)9798331507077

ISBN: (纸本)9798331507084

this paper presents a novel approach to Automatic Modulation Classification (AMC) that leverages a Gated Activation Patch Selection (GAPS) mechanism to enhance the efficiency of Transformer architectures. Our method addresses the computational challenges associated with Transformer-based AMC models by filtering out less informative signal patches before processing. the GAPS module utilizes convolutional layers to extract key features from the input signal and quantifies the importance of each patch through adaptive aggregation. By employing a Transformer encoder, the selected critical patches are transformed into embeddings, facilitating self-attention computations. Extensive experiments demonstrate that our method not only maintains competitive classification performance but also significantly reduces computational complexity, resulting in faster training and lower inference latency. Notably, our method achieves a 17.94% FLOPs reduction without any loss in performance, along with a similar degree of training acceleration, while the model's accuracy decreases by only 1.50% when the input signal length is reduced by 50%.

关键词： Training Accuracy Filtering Computational modeling Modulation Focusing Computer architecture Logic gates Transformers Feature extraction

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Low-Latency High-throughput Decoder of QC-LDPC Codes by Matrix Splitting

Low-Latency High-Throughput Decoder of QC-LDPC Codes by Matr...

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international conference on Wireless Communications and Signal processing (WCSP)

作者： Xinyu Zhong Shuaicong Gong Ming Jiang Chunming Zhao Southeast University

ISBN: (数字)9798350390643

ISBN: (纸本)9798350390650

As the continuously increasing demand of high data rate and lower transmission, many modern communication systems employ the LDPC coding scheme with ultra-high throughput decoder to achieve these challenging requirements. However, due to the implementation complexity of decoding algorithm, designing an ultra-high throughput decoder of LDPC codes still suffers many difficulties. therefore, we propose a FPGA-based LDPC decoder with partial parallel decoding, which splits and virtually supplements the parity-check matrix to achieve higher throughput and lower latency. Our proposed FPGA-based decoder can achieve a throughput of 6.072Gbps in 10 iterations for the highest rate 5G-LDPC code.

关键词： Wireless communication Signal processing algorithms Signal processing throughput Decoding Timing Table lookup Low latency communication Iterative decoding Field programmable gate arrays

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Reliability and Modelability Advantages of Distributed Switching for Reconfigurable 2D Processor Arrays

Reliability and Modelability Advantages of Distributed Switc...

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international conference and Workshop on Computing and Communication (IEMCON)

作者： Behrooz Parhami University of California Santa Barbara CA USA

ISBN: (数字)9781728184166

ISBN: (纸本)9781728184173

Processor arrays have been used, either as the main computation engine or as special-purpose adjuncts, for a variety of applications requiring very high performance. As the size of such an array increases, the possibility of processor malfunctions, leading to loss of computational capabilities, can no longer be ignored. While many switching architectures and reconfiguration algorithms have been proposed for building processor arrays, modeling of their reliability has been inadequately addressed. In this paper, I study differences between 2D processor arrays with centralized and distributed switching, pointing to advantages of the latter in terms of reliability, regularity, modularity, and VLSI realizability. As important side results, I formulate the notions of reliability inversion (a less reliable system prevailing over a more reliable one due to modeling uncertainties) and modelability (the property of a system that makes it possible to derive tight reliability bounds, thus making reliability inversion less likely).

关键词： Uncertainty Systematics Two dimensional displays Switches parallel processing Very large scale integration Reliability engineering

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A Scheduling Method for Avoiding Kernel Lock thrashing on Multi-cores

A Scheduling Method for Avoiding Kernel Lock Thrashing on Mu...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Yan Cui Weida Zhang Yu Chen Yuanchun Shi Department of Computer Science and Technology Tsinghua University China

Multi-core architectures have been adopted in various computing environments. Predictions based on Moore's Law state that thousands of cores can be integrated on a single chip within 10 years. To achieve better performance and scalability on multi-cores, applications should be multi-threaded, and therefore threads assigned on different cores can execute concurrently. However, lock contention in kernels can affect the scalability so significantly that the speedup decreases with the increasing number of cores (thrashing). Existing efforts to address this problem mainly focus on deferring lock thrashing, and therefore these techniques cannot prevent thrashing fundamentally. In this paper, we propose to use lock-aware scheduling to avoid thrashing. Our method detects thrashing on a per-thread basis and migrates contended threads to a smaller set of cores. the optimal number of cores is determined by maximizing the proposed normalized throughput model of migrated threads. the proposed method is implemented in Linux 2.6.29.4 and evaluated on a 32-core system. Experimental results on a series of lock-intensive micro- and macro-benchmarks show the effectiveness: for 3 of 5 workloads exhibiting thrashing behaviour, lock-aware scheduling can detect the speedup decrease accurately and sustain the maximal speedup, for the remaining 2 workloads, the performance can be improved greatly although the maximal speedup is not sustained, for 1 workload which does not suffer thrashing, the method introduces negligible runtime overhead.

关键词： Multicore processing Kernel Instruction sets Linux Benchmark testing throughput Complexity theory

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