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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是2741-2750 订阅

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Logic simulation using T-algorithm on network of workstations

Logic simulation using T-algorithm on network of workstation...

引用

IEEE Region 10 international conference TENCON

作者： S. Sundaram M.K. Srinivas Computer Aided Design Laboratory Supercomputer Education & Research Centre Indian Institute of Science Bangalore India

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulation algorithms is by exploiting the inherent parallelism in the sequential version. We propose a T-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network. the main objective has been to balance the computational load among the processors and at the same time reduce the communication to a bare minimum. We have achieved these by partitioning the circuit into cones containing gates in a fanout free region (FFR). Further, the cones of FFRs at the same level (having the same distance from primary inputs) are assigned by the master processor and communicated to the other workstations through the network. We have kept the balance on the computational load among slave processors by assigning a proper number of FFR cones, using a good heuristic. We have also shown that FFR partitioning reduces the amount of communication between the processors.< >

关键词： Workstations Circuit simulation Computational modeling Very large scale integration Digital circuits Logic design Logic circuits parallel processing Partitioning algorithms Integrated circuit interconnections

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On area-efficient low power array multipliers

On area-efficient low power array multipliers

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Yuke Wang Yingtao Jiang E. Sha Department of Computer Science University of Texas Dallas Richardson TX USA

Multiplication is one of the most critical operations in many computational systems. In this paper, we present an improved architecture for a multiplexer-based multiplication algorithm. Also through intensive HSPICE simulation, it has been shown in this paper that due to smaller internal capacitance, the multiplexer-based array multiplier outperforms the modified Booth multiplier in both speed and power dissipation by 13% to 26%. In addition, we demonstrate that using area-efficient full adder circuits (SERF and 10T) can help reduce the overall routing capacitance, resulting in less power consumption for multipliers built upon those adder circuits. therefore, a multiplexer-based multiplier following the suggested architecture, along with area-efficient full adder circuits, can be used for low power high performance parallel multiplier designs.

关键词： Adders Signal processing algorithms Energy consumption Digital signal processing Circuit simulation Capacitance Digital signal processors throughput Algorithm design and analysis Computer science

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Evolution of data management systems: from uni-processor to large-scale distributed systems 12

Evolution of data management systems: from uni-processor to ...

引用

Proceedings of the 10th international conference on Advances in Mobile Computing & Multimedia

作者： Abdelkader Hameurlain Paul Sabatier University Toulouse Cedex France

ISBN: (纸本)9781450313070

the purpose of this talk is to provide a comprehensive state of the art concerning the evolution of data management systems from uni-processor systems to large scale distributed systems. We focus our study on the query processing and optimization methods. For each environment, we recall their motivations and point out main characteristics of proposed methods, especially, the nature of decision-making (centralized or decentralized control for high level of scalability), adaptive level (intra-operator and/or inter-operator), impact of parallelism (partitioned and pipelined parallelism) and dynamicity (e.g. elasticity) of execution models.

关键词： query processing and optimization parallel and distributed database systems P2P systems heterogeneity data grid systems relational database systems data management autonomy data integration systems large scale dynamicity mobile agents

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Advance Quanvolutional Layers in Quantum Classical Hybrid Neural Networks for Image processing

Advance Quanvolutional Layers in Quantum Classical Hybrid Ne...

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international conference on Control, Automation and Robotics (ICCAR)

作者： Priyansh Singhal Piyush Joshi Department of Computer Science Indian Institute of Information Technology Sri City Chittoor India

ISBN: (数字)9798350373172

ISBN: (纸本)9798350373189

Convolutional neural networks (CNNs) are extensively employed for tasks such as image processing, employing a hierarchical feature extraction approach facilitated by convolutional layers. A recent trend explores quantum counterparts called Quanvolutional layers, utilizing random quantum circuits akin to convolutional filter layers. Our work advances this by introducing structured entanglement in quanvolutional layers using Basic and Strongly Entangled Layers. Unlike random circuit approaches, these layers have defined structures and high entanglement, requiring minimal error correction. We evaluated their performance on MNIST dataset, comparing various techniques like traditional CNNs, Quanvolutional Neural Networks (QNNs) with Random quantum circuits, basic entangled layers, strongly entangled layers. Structured entanglement shows promise in improving feature extraction for QNNs, providing insights into their understanding. Our work explores the use of structures quantum layers in constructing quantum-classical hybrid architectures and evaluates their performance. Future research may explore scalability and applicability in complex datasets and integration with other quantum computing techniques for enhanced performance and versatility.

关键词： Training Quantum entanglement Scalability Neural networks Process control Feature extraction Error correction

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Fiber Optics Transforms 10th

Fiber Optics Transforms

引用

Proceedings of 2008 10th Anniversary international conference on Transparent Optical Networks

作者： Michela Svaluto Moreolo Gabriella Cincotti University Roma Tre Via della Vasca navale 84 00146 Rome Italy

ISBN: (纸本)9781424426256

We give fiber or planar lightwave circuit (PLC) architectures to implement the Discrete Fourier Transform (DFT) and the Discrete Hartley Transform (DHT) directly in the optical domain. In both cases, we present a recursive approach for the decimation-in-frequency algorithm, considering parallel and serial input configurations. We also describe PLC devices for high-speed optical filtering and data compression, based on Discrete Wavelet Transforms (DWT) and Discrete Cosine Transform (DCT).

关键词： discrete transforms fiber optics planar lightwave circuits asymmetric couplers optical signal processing

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DEEP IMAGE CLUSTERING USING CONVOLUTIONAL AUTOENCODER EMBEDDING WIth INCEPTION-LIKE BLOCK

DEEP IMAGE CLUSTERING USING CONVOLUTIONAL AUTOENCODER EMBEDD...

引用

IEEE international conference on Image processing

作者： Qiang Wang Jiaqing Xu Rongchun Li Peng Qiao Ke Yang Shijie Li Yong Dou National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer National University of Defense Technology Changsha China

Image clustering is one of the challenging tasks in machine learning, and has been extensively used in various applications. Recently, various deep clustering methods has been proposed. these methods take a two-stage approach, feature learning and clustering, sequentially or jointly. We observe that these works usually focus on the combination of reconstruction loss and clustering loss, relatively little work has focused on improving the learning representation of the neural network for clustering. In this paper, we propose a deep convolutional embedded clustering algorithm with inception-like block (DCECI). Specifically, an inception-like block with different type of convolution filters are introduced in the symmetric deep convolutional network to preserve the local structure of convolution layers. We simultaneously minimize the reconstruction loss of the convolutional autoencoders with inception-like block and the clustering loss. Experimental results on multiple image datasets exhibit the promising performance of our proposed algorithm compared with other competitive methods.

关键词： Convolutional codes Convolution Clustering algorithms Image reconstruction Decoding Clustering methods Task analysis

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Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

Design of a multi GBPS Single Carrier digital baseband for 6...

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international conference on Field Programmable Logic and Applications

作者： Surendra Guntur Feike Jansen Jan Hoogerbrugge Lotfi Abkari Eric Vos NXP Semiconductors Eindhoven Netherlands NXP Semiconductors Leuven Belgium

this paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. the baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. the demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

关键词： Baseband Field programmable gate arrays Receivers throughput Radio frequency parallel processing Application specific integrated circuits

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FPGA accelerated tate pairing based cryptosystems over binary fields

FPGA accelerated tate pairing based cryptosystems over binar...

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IEEE international conference on Field-Programmable Technology (FPT)

作者： Chang Shu Soonhak Kwon Kris Gaj Department of Electrical & Computer Engineering George Mason University Fairfax VA USA Department of Mathematics Sungkyunkwan University Suwon South Korea

Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. For our implementation we have chosen the binary elliptic case because of the simple underlying algorithms and efficient binary arithmetic. In this paper, we propose a new FPGA-based architecture of the Tate pairing-based computation over the binary fields F 2239 and F 2283 . Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 10-to-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. At the same time, an improvement in the product of latency by area by a factor between 12 and 46 for an equivalent type of implementation has been achieved

关键词： Field programmable gate arrays Acceleration Public key cryptography Identity-based encryption Elliptic curve cryptography Computer architecture Security Delay Identity management systems parallel processing

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Efficient Management and Intelligent Fault Tolerance for HPC Interconnect Networks

Efficient Management and Intelligent Fault Tolerance for HPC...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Jijun Cao Mingche Lai Zhang Luo jiaqing Xu Zhengbin Pang College of Computer National Laboratory for Parallel and Distributed Processing ChangSha China

ISBN: (纸本)9781728125848

Interconnect Network is the key component in high performance computing system. With the incoming era of Exa-Scale (10 18 FLOPS) computing, designing large scale interconnect networks is facing with serious challenges in network management and fault tolerance. To construct higher performance and more reliable interconnect networks, we propose an efficient and intelligent network management architecture for indirect interconnect networks. this paper emphatically introduces the network management architecture, the in-band management channels in the Network Interface Chips (NIC) and Network Routing Chips (NRC) respectively, efficient centralized network management approach, distributed intelligent faulttolerant routing management, and so on. Based on the prototype system, the Control and Status Registers (CSR) accessing latency performance of in-band network management is evaluated. Also based on a customized simulation model for indirect interconnect networks, the typical distributed fault-tolerant scenes are tested. the experiment results show the in-band network management can averagely achieves 716 times improvements than the out of-band network management. Moreover, by running heuristic algorithms to automatically reconstruct routing tables for failure links or routers, the intellectual network management Engine can achieve fault-tolerant routing to maximizing network performance.

关键词： High performance computing system Interconnect network Network management Fault tolerate Network management Fault tolerance High Performance Computing unified network management architecture Network Network routing

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Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

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Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

the desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. these systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. this new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

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