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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Neural Architecture Search Based on Tabu Search and Evolutionary Algorithm

Neural Architecture Search Based on Tabu Search and Evolutio...

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IEEE international conference on Cyber Technology in Automation, Control, and Intelligent Systems

作者： Zhun Fan Zhoubin Long Wenji Li Zhaojun Wang Zhi Yang Liu Wang Guangdong Province Engineering college Shantou University Shantou Guangdong China

Most existing optimization methods for neural architecture search (NAS), including evolutionary algorithms, reinforcement learning and gradient-based approaches, have not employed memory strategies explicitly, which may lack of efficiency when searching neural architectures. To solve this issue, we propose a new NAS approach by using an evolutionary algorithm which employs a tabu mechanism to help to improve the search efficiency. To be more specific, the individuals of parent population are selected by tournament selection and tabu list. the tournament selection select parent population according to the accuracy of each individual. And the tabu mechanism builds a tabu list to record the chosen operations in the last previous search process, which employs a search memory mechanism to improve the efficiency explicitly. To confirm the superior performance of our approach, a well-designed surrogate model is used to accelerate the process of performance evaluation on CIFAR-10. the comprehensive experimental results show that the proposed method can reach to 2.48% error rate with about 2 GPU days, which demonstrates the superiority of the suggested method.

关键词： Performance evaluation Error analysis Sociology Memory management Graphics processing units Optimization methods Evolutionary computation

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5 Gbit/s real-time processing using π/4-shift DQPSK for bidirectional radio-over-fibre system

5 Gbit/s real-time processing using π/4-shift DQPSK for bid...

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international conference on Transparent Optical Networks

作者： Kai Habel Luz Fernandez del Rosal Stefan Weide Jonas Hilt Volker Jungnickel Robert Elschner Colja Schubert Felix Frey Johannes Karl Fischer Ronald Freund Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Berlin Germany

Future converged fixed-mobile networks need high-speed radio links in deployment scenarios where fibre is not available or too expensive. In this paper, we present a field-programmable gate array (FPGA)-based real-time transmission system using standard 10G Ethernet interfaces. the system comprises two parallel complex-valued data channels in each direction. Standard FPGAs and low-cost multi-channel analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs) have been used. For enhanced robustness and optimal usage of the power amplifier, π/4-shift differential quaternary phase-shift keying (DQPSK) modulation is used. All digital signal processing routines for synchronization, equalization, forward error correction etc. have been fully implemented and tested. Using a protocol analyzer, error-free bidirectional transmission of Ethernet frames at 5 Gbit/s is verified. Error-vector magnitude (EVM) values below -30 dB indicate that even higher speeds could be realized.

关键词： Synchronization Field programmable gate arrays Bit error rate Signal processing algorithms Boards Forward error correction Signal to noise ratio

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Hierarchical Filter and Refinement System Over Large Polygonal Datasets on CPU-GPU

Hierarchical Filter and Refinement System Over Large Polygon...

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international conference on High Performance Computing

作者： Yiming Liu Jie Yang Satish Puri Computer Science Dept. Marquette University

ISBN: (纸本)9781728145365

In this paper, we introduce our hierarchical filter and refinement technique that we have developed for parallel geometric intersection operations involving large polygons and polylines. the inputs are two layers of large polygonal datasets and the computations are spatial intersection on a pair of cross-layer polygons. these intersections are the compute-intensive spatial data analytic kernels in spatial join and map overlay computations. We have extended the classical filter and refine algorithms using PolySketch Filter to improve the performance of geospatial computations. In addition to filtering polygons by their Minimum Bounding Rectangle (MBR), our hierarchical approach explores further filtering using tiles (smaller MBRs) to increase the effectiveness of filtering and decrease the computational workload in the refinement phase. We have implemented this filter and refine system on CPU and GPU by using OpenMP and OpenACC. After using R-tree, on average, our filter technique can still discard 69% of polygon pairs which do not have segment intersection points. PolySketch filter reduces on average 99.77% of the workload of finding line segment intersections. PNP based task reduction and Striping algorithms filter out on average 95.84% of the workload of Point-in-Polygon tests. Our CPU-GPU system performs spatial join on two shapefiles, namely USA Water Bodies and USA Block Group Boundaries with 683K polygons in about 10 seconds using NVidia Titan V and Titan Xp GPU.

关键词： Spatial databases Graphics processing units Computational geometry Large scale integration Filtering algorithms Tiles

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StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs

StencilStream: A SYCL-based Stencil Simulation Framework Tar...

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international conference on Field Programmable Logic and Applications

作者： Jan-Oliver Opdenhövel Christoph Alt Christian Plessl Tobias Kenter Department of Computer Science Paderborn Center for Parallel Computing Paderborn University Friedrich Alexander Universität Erlangen

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Although High-Level Synthesis has dramatically improved the usability of FPGAs in High-Performance Computing applications, it still requires much experience to create well-performing FPGA designs. We introduce the stencil simulation framework StencilStream to separate the concerns of performance engineers and domain scientists. We have formulated our performance-oriented stencil simulation designs for FPGAs along with their management code as C++ templates using SYCL language features. Application developers instantiate these templates with their concrete stencil code and obtain a complete application with little management overhead. In this work, we describe the most interesting API features and the two backend architectures of StencilStream, along with their corresponding performance models. We then evaluate the performance of the architectures using three manually implemented sample applications and highlight the real-world usability of StencilStream further with shallow water simulations obtained from a code-generation flow. Compiled with Intel oneAPI for an Intel Stratix 10 GX 2800 target FPGA, the best-performing sample design exceeds a throughput of 1 TFLOPS.

关键词： Productivity Codes High performance computing Graphics processing units Computer architecture throughput Logic Usability Field programmable gate arrays Engines

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Parameter prediction for unseen deep architectures 21

Parameter prediction for unseen deep architectures

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Proceedings of the 35th international conference on Neural Information processing Systems

作者： Boris Knyazev Michal Drozdzal Graham W. Taylor Adriana Romero-Soriano University of Guelph and Vector Institute for Artificial Intelligence Facebook AI Research University of Guelph and Vector Institute for Artificial Intelligence and Canada CIFAR AI Chair Facebook AI Research and McGill University

ISBN: (纸本)9781713845393

Deep learning has been successful in automating the design of features in machine learning pipelines. However, the algorithms optimizing neural network parameters remain largely hand-designed and computationally inefficient. We study if we can use deep learning to directly predict these parameters by exploiting the past knowledge of training other networks. We introduce a large-scale dataset of diverse computational graphs of neural architectures – DEEPNETS-1M– and use it to explore parameter prediction on CIFAR-10 and ImageNet. By leveraging advances in graph neural networks, we propose a hypernetwork that can predict performant parameters in a single forward pass taking a fraction of a second, even on a CPU. the proposed model achieves surprisingly good performance on unseen and diverse networks. For example, it is able to predict all 24 million parameters of a ResNet-50 achieving a 60% accuracy on CIFAR-10. On ImageNet, top-5 accuracy of some of our networks approaches 50%. Our task along with the model and results can potentially lead to a new, more computationally efficient paradigm of training networks. Our model also learns a strong representation of neural architectures enabling their analysis.

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Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL

Research on Mahalanobis Distance Algorithm Optimization Base...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Qingchun Xie Yunquan Zhang Haipeng Jia Yongquan Lu High Performance Computing Center Communication University of China Beijing China Chinese Academy of Sciences Institute of Software Beijing China Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9781479961245

Mahalanobis distance algorithms has been widely used in machine learning and classification algorithms, and it has an important practical significance in improving the performance of some applications through GPU, especially in some applications with high real-time demand. However, due to the complexity of the GPU hardware architectures, how to complete the algorithm optimization and achieve high performance portability on different GPU platforms is still a hard work. the redundant calculation of traditional Mahalanobis distance algorithm is very large and is hard to implement parallel. In this paper, we not only throw light on the universal ways to properly map mature algorithms to GPU devices to implement the Mahalanobis distance, such as fixed number of workgroups and vectorization, but also put forward five valuable methods of performance optimization on heterogeneous computing platforms, such as two-dimension NDRange workgroup arrangement, Uberkernel, binary reduction with the help of LDS register in one workgroup. Furthermore, We also demonstrate the high performance of our implementation by comparing it with a well-optimized CPU version from OpenCV library. Experimental results show that speedup reaches up 10.59 times on NVIDIA GPU C2050, 8.55 times on AMD HD5850 and 16.08 times on HD7970. the last experimental results verified the effectiveness of optimization methods which we proposed.

关键词： Graphics processing units Instruction sets Synchronization Optimization Vectors Zinc Computer architecture

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A FPGA-based accelerator implementaion for YOLOv2 object detection using Winograd algorithm

A FPGA-based accelerator implementaion for YOLOv2 object det...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Peng Lv Wei Liu Jinghui Li School of Computer Engineering and Science Shanghai University Shanghai China

ISBN: (纸本)9781665423144;9781665446235

Convolutional neural networks (CNNs) are used in many computer vision applications and the computational complexity of CNN has increased greatly. Since CPUs can hardly provide the massive parallelism required by CNNs, many hardware accelerators, such as GPU, FPGA, and ASIC, have been developed to improve the performance of CNNs. Of these designs, FPGA-based accelerators have become a special option due to their advantages of high flexibility, low power consumption and extensive DSP resources. In this paper, an OpenCL-based CNN accelerator is designed for FPGA and a variety of model compression techniques are applied to the YOLOv2 model. the accelerator uses the Winograd algorithm to implement convolution efficiently and reduce the number of multiplications by 38% to 60% for YOLOv2 model, also this design makes full use of the available memory access bandwidth and DSP resources. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results on YOLOv2 network show a 1.2x~1.9x speedup compared with im2col convolution algorithms and the performance of our FPGA design can reach 10ms per image in terms of latency, compared to 16ms per image with Nvidia Tesla V100 GPU.

关键词： Power demand Convolution Memory management Graphics processing units Random access memory Object detection parallel processing

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Solder Ball Height Measurement by Projection Method

Solder Ball Height Measurement by Projection Method

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Measurement Touch the World——IEEE 2011 10th international conference on Electronic Measurement & Instruments(ICEMI’2011)

作者： Qin Jingwen,Chen Yun,Wang Fuliang State Key Laboratory of High Performance and Complex Manufacturing College of Mechanical and Electrical Engineering,Central South University Changsha 410083,China

the height uniformity of solder ball is an important aspect of solder joint reliability for BGA package.A novel optical method for solder ball height inspection was proposed.A parallel beam was used to illuminate the solder ball,and the shadow of ball was used to measure its height.A machine vision system has been designed to realize this *** ball image and shadow image are obtained by two time lightning and *** image process algorithms are developed to evaluate the center and radius of solder balls from the solder ball image,and the projection length from the shadow *** those information form images,the height of a solder ball and coplanarity is *** experimental results obtained from this new method show good agreement with that obtained by SEM and Veeco.

关键词： ball grid array optical shadow height measurement machine vision image processing.

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Lagrangian Approach for the Study of Heat Transfer in a Nuclear Reactor Core Using the SPH Methodology 10th

Lagrangian Approach for the Study of Heat Transfer in a Nucl...

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10th international conference on Supercomputing, ISUM 2019

作者： Pahuamba-Valdez, F. Mayoral-Villa, E. Alvarado-Rodríguez, C.E. Klapp, J. Gómez-Torres, A.M. Del Valle-Gallegos, E. Instituto Nacional de Investigaciones Nucleares Carretera México – Toluca s/n La Marquesa OcoyoacacEstado de México52750 Mexico Instituto Politécnico Nacional Escuela Superior de Física y Matemáticas Instituto Politécnico Nacional Ciudad de México Mexico Departamento de Ingeniería Química División de Ciencias Naturales y Exactas Universidad de Guanajuato Noria Alta s/n GuanajuatoGuanajuato36050 Mexico

ISBN: (纸本)9783030380427

Numerical modeling simulations and the use of high-performance computing are fundamental for detailed safety analysis, control and operation of a nuclear reactor, allowing the study and analysis of problems related with thermal-hydraulics, neutronic and the dynamic of fluids which are involved in these systems. In this work we introduce the bases for the implementation of the smoothed particle hydrodynamics (SPH) approach to analyze heat transfer in a nuclear reactor core. Heat transfer by means of convection is of great importance in many engineering applications and especially in the analysis of heat transfer in nuclear reactors. As a first approach, the natural convection in the gap (space that exists between the fuel rod and the cladding) can be analyzed helping to reduce uncertainty in such calculations that usually relies on empirical correlations while using other numerical tools. the numerical method developed in this work was validated while comparing the results obtained in previous numerical simulations and experimental data reported in the literature showing that our implementation is suitable for the study of heat transfer in nuclear reactors. Numerical simulations were done with the DualSPHysics open source code that allows to perform parallel calculations using different number of cores. the current implementation is a version written in CUDA (Compute Unified Device Architecture) that allows also the use of GPU processors (Graphics Processor Unit) to accelerate the calculations in parallel using a large number of cores contained in the GPU. this makes possible to analyze large systems using a reasonable computer time. the obtained results verified and validated our method and allowed us to have a strong solver for future applications of heat transfer in nuclear reactors fuel inside the reactor cores. © Springer Nature Switzerland AG 2019.

关键词： Graphics processing unit

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TPC-NAS: Simple and Effective Neural Architecture Search Based on Total Path Count

TPC-NAS: Simple and Effective Neural Architecture Search Bas...

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IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Ming-Shan Huang Pi-Chuan Chen Tzi-Dar Chiueh National Taiwan University Taipei Taiwan

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

With the explosive growth of neural network (NN) research and application areas, there is a pressing need to automate the NN model search process in order to attain optimal performance. Nevertheless, existing neural architecture search (NAS) algorithms are time-consuming, resource-intensive, and predominantly tailored for image-related applications. this paper presents the Total Path Count (TPC) score, a straightforward yet highly efficient accuracy predictor solely reliant on the architectural information of a model. the effectiveness of the TPC score is underscored by a robust rank correlation of 0.96 between TPC scores and the accuracies of CIFAR100 architectures. We further introduce TPC-NAS, a zero-shot NAS method that can complete a NAS task in under five CPU minutes without training and inference. TPC-NAS has found wide-ranging applications and it outperforms many other NAS solutions. In image classification, TPC-NAS achieves 78.3% ImageNet top-1 accuracy with 399M FLOPs, while in object detection, it improves mAP by at least 2% over other NAS-derived models. Moreover, TPC-NAS successfully discovers a super-resolution architecture with < 300K parameters and achieves 32.09dB PSNR. In NLP, TPC-NAS delivers a model that matches tinyBERT’s FLOPs but outperforms it by almost 10% in accuracy. these experiments illustrate TPC-NAS’s ability to rapidly generate high-performance CNN/transformer architectures for various applications.

关键词： Training Accuracy Superresolution Object detection Artificial neural networks Natural language processing Central processing Unit

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