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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Dominik Walter thomas Adamtschuk Frank Hannig Jürgen Teich Department of Computer Science Hardware/Software Co-Design Friedrich-Alexander-Universitat Erlangen-Niirnberg (FAU) Germany

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

LU decomposition is a widely used application for solving systems of linear equations. It involves decomposing a given matrix into a lower and upper triangular matrix. But if the matrix size is large, using a block-based LU decomposition on smaller submatrices can be advantageous. this approach allows for an adaptation to a target architecture's memory and computing resources. In this paper, we analyze different strategies for mapping block LU decompositions onto Tightly Coupled Processor Arrays (TCPAs). Each decomposition introduces a dependence graph of matrix operations of smaller size: an unblocked LU decomposition, a triangular matrix solver, and a general matrix-matrix multiplication. First, we propose one piecewise regular algorithm for each corresponding loop nest, analyze its complexity, and then explore various reuse schemes for configuration, data, and synchronization. It will be shown that these schemes have a significant impact on the execution time of the entire algorithm and must be considered by the scheduling approach that governs the individual loop program invocations. Our performance analysis of the mapped block LU decomposition shows a maximal speedup of 12 on a TCPA of size $4\times 4$ compared to a CPU, and a measured speedup of 10 measured on an FPGA-based SoC.

关键词： Schedules Runtime Systems architecture Transforms parallel processing Size measurement Complexity theory

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Detection of Arc in the Transmission Power Lines

Detection of Arc in the Transmission Power Lines

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international conference on Environment and Electrical Engineering

作者： Pawel Kostyla Department of Electrical Engineering Wroclaw University of Technology

ISBN: (纸本)9781424487790

Automatic one-and three-phase re-closing power lines, after short circuit shutdown, is a very effective way to improve the reliability of power delivery. Re-closing while the fault is not cleared can be dangerous for some electrical appliances. To prevent re-closing of a short circuit a method allowing stable arc detection has developed. the method is based on the estimation of real-time parameters in voltage signals and an analysis of error estimation. A neural network has been proposed to solve the problem in real time.

关键词： Neural network Signal processing Optimization problem Arc voltage parallel algorithms

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Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors

Integrating Compiler and System Toolkit Flow for Embedded VL...

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IEEE international conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Chi Wu Kun-Yuan Hsieh Yung-Chia Lin Chung-Ju Wu Wen-Li Shih S. C. Chen Chung-Kai Chen Chien-Ching Huang Yi-Ping You Jenq Kuen Lee Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. this creates challenges to deploy software toolkits for new embedded DSP processors. this article presents our methods and experiences to develop software and toolkit flows for PAC (parallel architecture core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger and DSP micro-kernels. We first retarget open research compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assembler are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dual-core environments. the footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations

关键词： VLIW Digital signal processing Registers Encoding Software tools Assembly Application software Embedded software parallel architectures Pipelines

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Off-Chip Congestion Management for GPU-based Non-Uniform processing-in-Memory Networks

Off-Chip Congestion Management for GPU-based Non-Uniform Pro...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Kishore Punniyamurthy Andreas Gerstlauer The University of Texas at Austin

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

Advancements in packaging and 3D-stacking technology have enabled novel non-uniform processing-in-memory (NUPIM) architectures integrating a network of hybrid modules each with varying sizes and proportions of compute and memory. In such systems, network congestion can have a significant impact on performance and energy-efficiency scaling. At the same time, NUPIM systems often have strict power and thermal constraints, where traditional routing/redundancy or buffering based approaches to reduce congestion cannot be *** this paper, we propose a low-overhead yet scalable scheme for congestion management in off-chip networks of emerging GPU-based NUPIM systems. We note that congestion in NUPIM networks exhibits a form of tree saturation in which individually congested links form congested paths, where congestion effects due to back pressure vary across paths. Additionally, memory responses can have different performance impact due to memory divergence. Our approach exploits differences in performance impact of NUPIM traffic to mitigate congestion effects. We dynamically track congested paths and divergent data to manage priorities and accelerate performance-critical traffic. We further use critical paths knowledge to dynamically manage link widths and save I/O *** show that our congestion management outperforms a configuration with double the number of virtual channels and buffers indicating its effectiveness in managing congestion under stringent constraints. It improves performance by 15% (and up to 31%) over baseline and 10% (and up to 29%) against a memory distance based approach for congestion-affected benchmarks. Our scheme reduces 78% of I/O energy on average and up to 29% of system energy across all benchmarks.

关键词： Benchmark testing Delays Market research Systems architecture Packaging Memory management

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parallel super-resolution reconstruction based on neighbor embedding technique

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2015年 9156卷 134-143页

作者： Moustafa, Marwa Ebied, Hala M. Helmy, Ashraf Nazamy, Taymoor M. Tolba, Mohamed F. Faculty of Computer and Information Sciences Ain Shams University Cairo Egypt Data Reception Analysis and Receiving Station Affairs National Authority for Remote Sensing and Space Science Cairo Egypt

Super Resolution (SR) is a technique to recover a high-resolution (HR) image from different noisy low resolution (LR) images. the missing highfrequency components in LR images should be restored correctly in HR image. Because of the extensive size of satellite images, the utilize to parallel algorithms can accomplish results more quickly with accurate results. this paper proposes an accelerated parallel implementation for an example based super-resolution algorithm, Neighbor Embedding (NE), using GPU. the NE trains the dictionary with patches obtained from a single image in the training phase. Euclidean distances are used to obtain the optimal weights that will be used in the construction of high-resolution images. Compute Device Unified Architecture (CUDA) by NVidia’s has been used to implement the proposed parallel NE. Different experiments have been carried out on a synthetic test image and satellite test image. the proposed GPU implementation of the NE was benchmarked against the serial implementation. the experimental results show that the speed of the implementation depends on the image size. the speed of the GPU implementation compared to the serial one using CPU ranged from 20× for small images to more than 30× for large image size. © Springer international Publishing Switzerland 2015.

关键词： Graphics processing unit

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Real-time Face Detection Algorithm Using GPU

Real-time Face Detection Algorithm Using GPU

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2011 IEEE 12th international conference on Computer-Aided Industrial Design & Conceptual Design

作者： Zhongyuan FENG School of Software Engineering Tongji University Shanghai,China Jinyuan JIA,Feipeng ZHAO School of Software Engineering Tongji University Shanghai,China

processing of human faces plays an important part in various domains such as biometrics,video surveillance, information security,interactive video games and human computer interaction;most of them require real-time and interactive *** this paper,we present a new GPU implementation of human face detection algorithm based on *** with CPU version,it extraordinarily improves the performance and detection ***,it also implements high acceleration *** the difference of other GPU-based algorithms,we have done many other new parallelization works independently,such as parallel processing of Haar wavelet,cascade classifier and different sizes or positions of detected *** data show that our proposed method achieves better *** performance of GPU version is enhanced,detection speed is accelerated up to 10 to 42 times compared with CPU-based implementation,also real-time level constraints is met as well.

关键词： face detection AdaBoost parallel GPU real-time

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Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler for wireless endoscopy capsule

Low complexity and efficient architecture of 1D-DCT based Co...

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IEEE SSD international Multi-conference on Systems, Signals and Devices

作者： N. Jarray M. Elhaji A. Zitouni Faculty of Sciences of Monastir Electronic and Micro-Electronic Laboratory Tunisa Monastir University Tunisia University of Dammam Saudi Arabia

Due to the power limitation and the small size condition of the wireless capsule endoscopy, therefore the principal defiance is to reduce the area and the power consumption. the aim is to preserve acceptable image reconstruction and coding. In this paper, we present a Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler technique for wireless capsule endoscopy. Our improvement over the original algorithm is performed in CORDIC part. this brings us to reduce the number of addition operations from 18 to 10. As a result, the number of addition is reduced from 38 to 30 operations in the main algorithm. Also, to more ameliorate our results, we used Modified Carry look Ahead adder (MCLA) and Carry Save Adder (CSA) adder which are characterized by low power and high speed compared to classical Carry Look Ahead adder (CLA). Our aim is to provide an optimized architecture in terms of area and power consumption. the proposed design has been implemented on FPGA. Compared to other architectures, the proposed architecture has not only reduced the computation complexity, but also the area and the power consumption. It should be noted that the proposed DCT architecture is very suitable for low-power and high-quality codecs, especially for battery-based systems.

关键词： Discrete cosine transforms Computer architecture Adders Signal processing algorithms Wireless communication Endoscopes Complexity theory

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Scheduling 3D printers with multiple printing alternatives

Scheduling 3D printers with multiple printing alternatives

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IEEE international conference on Automation Science and Engineering (CASE)

作者： Jun Kim Sang-Soo Park Hyun-Jung Kim Department of Industrial Engineering Sungkyunkwan University Suwon Korea

We examine a 3D printer scheduling problem with products that have multiple printing alternatives for makespan minimization. When 3D printers are used as processing machines, products can be printed in either a complete form or as parts, which are assembled later, and the printed parts can also have different forms. Hence, products have multiple printing alternatives, each of which consists of different types and numbers of parts, and the total printing time of a product depends on the printing alternatives. therefore, we need to select the best printing alternative for each product and assign the corresponding parts to 3D printers efficiently so that the makespan of producing all of the products can be minimized. We first propose a mathematical model and then develop a genetic algorithm to address this problem. We experimentally show that the average difference between the makespan from the genetic algorithm and its lower bound is less than 2%, even for 50 jobs with 10 3D printers.

关键词： Printers three-dimensional displays Printing parallel machines Job shop scheduling Genetic algorithms Schedules

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Implementation of high speed data transfer serialized 128/130bit encoding algorithm using 90nm technology

Implementation of high speed data transfer serialized 128/13...

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international conference on Advanced Computing and Communication Systems (ICACCS)

作者： F. Mhaboobkhan M. Fathimaparveen K. Gokila P. Logapriya Department of Electronics and Communication Engineering P.A College of Engineering and Technology Coimbatore

In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a faster rate, reduces the pin counts which in turn lead to much smaller devices in an integrated circuit compared to parallel communication. Line coding can potentially help in high data transfers. In this paper 128b/130b line coding algorithm has been proposed which has the double the payload of conventional 64b/66b encoding technique, with same number of preamble bits. this increases the data transfer rate drastically. the polynomial for the scrambler has been used from IEEE clause. the proposed 128b/130b encoding algorithm has been coded using Verilog and simulated using Quartus II 9.0v .the parameters such as Setup time, Hold time, Maximum frequency, power and slack for 8b/10b, 64b/66b and 128b/130b has been compared and tabulated. the layout has been designed for 128b/130b using Cadence Encounter 14.26 tool. the comparison shows that proposed algorithm has higher data rate at the expense of increase in hardware utilization.

关键词： Encoding Registers Timing Payloads Signal processing algorithms Digital communication

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Semi-Optimal MicroService Placement in the Fog with Quality of Service (QoS) Awareness

Semi-Optimal MicroService Placement in the Fog with Quality ...

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international conference on Control, Decision and Information Technologies (CoDIT)

作者： Amira Rayane Benamer Audensiel Paris France

ISBN: (数字)9798350373974

ISBN: (纸本)9798350373981

the proliferation of connected devices has catalyzed a shift towards intelligent systems reliant on real-time analytics for decision-making. While Cloud computing offers a mature service infrastructure, the transfer of vast data volumes for processing introduces challenges such as network congestion and latency, hampering real-time requirements. Edge/Fog computing emerges as a solution, enabling data processing and hosting lightweight learning models closer to users at the network edge. However, unlike the Cloud, which exhibits high resource elasticity with a limited number of resource nodes, Edge/Fog resources are widely distributed with high density, characterized by their heterogeneity and limited capacities. To optimize the deployment of applications with diverse resource and latency requirements, a strategic approach to application placement across Edge/Fog and Cloud computing environments is essential. this strategy must carefully balance application-specific needs, latency sensitivity, and operational cost minimization. To this end, we begin by formulating the placement problem as a linear program, focusing on microservice applications. We then propose a hybrid approach that combines k-means clustering for grouping Edge/Fog nodes (based on physical location) with the formulated linear model to enhance computational efficiency. the linear model is developed using the CPLEX solver and validated using real-world datasets of Edge/Fog node and user distributions. the findings unequivocally demonstrate that the clustering step leads to significantly decreased decision placement times, all while maintaining a high standard of solution quality. these results provide a promising avenue for deploying optimal models directly at the network’s edge, enabling optimal application placement decisions while adhering to problem constraints.

关键词： Cloud computing Costs Sensitivity Computational modeling Microservice architectures Quality of service Computer architecture Real-time systems Standards Testing

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