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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是321-330 订阅

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Automatic code generation for SIMD DSP architectures: An algebraic approach

Automatic code generation for SIMD DSP architectures: An alg...

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4th international conference on parallel Computing in Electrical Engineering (PARELECT 2004)

作者： Robelly, JP Cichon, G Seidel, H Fettweis, G Dresden Univ Technol Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)0769520804

Driven by the ever increasing algorithm complexity on the field of mobile communications systems, SIMD DSP architectures have emerged as an approach that offers the necessary processing power at reasonable levels of die size and power consumption. However, this kind of DSP architectures imposes new challenges for programmers, since algorithms have to be designed to exploit the available parallelism on the processor. Taking as a starting point an algebraic framework that captures the SIMD computational model, we report in this paper about our efforts to design and automatically generate object code for our family of DSP architectures independent of the available SIMD parallelism. We show how these algebraic structures can be used as a high level programming language that offers a unified approach to design and describe algorithms using SIMD parallelism. Moreover, we show how these algebraic structures offer concise rules for the automatic code generation.

关键词： Signal processing

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An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. this is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. this hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

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parallel Object-Oriented Implementation of the TestU01 Statistical Test Suites 10

Parallel Object-Oriented Implementation of the TestU01 Stati...

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IEEE 10th international conference on Intelligent Computer Communication and processing (ICCP)

作者： Suciu, Alin Toma, Radu Alexandru Marton, Kinga Tech Univ Cluj Napoca Dept Comp Sci Cluj Napoca Romania

ISBN: (纸本)9781479965694

Evaluation of the randomness quality of a random number generator requires an efficient suite of statistical tests which takes advantage of the processing power of today's multi-core processing power in order to cope with the large amount of data to be processed. While, in theory, most complex processing algorithms can be tuned for concurrent execution, the solution will eventually reach a state in which a compromise needs to be made between the overall performance and the configurability and usability of the application. Our solution is based on completely re-designing the TestU01 architecture to include the notion of parallel computing as part of the general requirements, and not as a tool used for increasing performance. Implementation of this design is done using concepts from the object-oriented paradigm, and uses the. NET Task parallel Library. Experimental results show that the parallel OOP based implementation of the TestU01 library not only obtains similar results as the previous parallel version, but in some cases a better speedup is obtained.

关键词： random number sequences statistical tests parallel implementation object-oriented paradigm TestU01

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A GPU implementation for two MIMO-OFDM detectors

A GPU implementation for two MIMO-OFDM detectors

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2010 10th international conference on Embedded Computer Systems: architectures, Modeling and Simulation, IC-SAMOS 2010

作者： Nyländen, Teemu Janhunen, Janne Silvén, Olli Juntti, Markku Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781424479382

Two real-valued signal models based on selective spanning with fast enumeration (SSFE) and layered orthogonal lattice detector (LORD) algorithms are implemented on a Nvidia graphics processing unit (GPU). A 2 x 2 multiple-input multiple-output (MIMO) antenna system with 16-quadrature amplitude modulation (16-QAM) is assumed. the chosen level update vector for SSFE is based on computer simulation results carried out in MATLAB environment. We implemented the algorithms with Nvidia Quadro FX 1700 GPU and achieved a throughput of 36.06 Mbps for SSFE and 16.8 Mbps for LORD. the results show that the general-purpose graphics processing unit (GPGPU) has the potential to achieve high throughput, presuming a detection algorithm that allows efficient parallel processing. the latency of the control code and partial Euclidean distance (PED) calculations are very small-scale, but the latency of memory loads and stores to the GPUs global memory are significant. We also compare results from the trellis based detector implementation for GPU, where a more powerful GPU and a different detection algorithm are used. the GPUs offer superior computing power and programmability compared to the application specific software defined radio (SDR) designs implemented so far. ©2010 IEEE.

关键词： Graphics processing unit

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algorithms and architectures for parallel processing 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Yang Xiang Wanlei Zhou Alfredo Cuzzocrea Michael Hobbs

ISBN: (数字)9783642246692

ISBN: (纸本)9783642246685

this two volume set LNCS 7016 and LNCS 7017 constitutes the refereed proceedings of the 11th international conference on algorithms and architectures for parallel processing, ICA3PP 2011, held in Melbourne, Australia, in October 2011. the second volume includes 37 papers from one symposium and three workshops held together with ICA3PP 2011 main conference. these are 16 papers from the 2011 international Symposium on Advances of Distributed Computing and Networking (ADCN 2011), 10 papers of the 4th IEEE international Workshop on Internet and Distributed Computing Systems (IDCS 2011), 7 papers belonging to the III international Workshop on Multicore and Multithreaded architectures and algorithms (M2A2 2011), as well as 4 papers of the 1st IEEE international Workshop on parallel architectures for Bioinformatics Systems (HardBio 2011).

关键词： Algorithm Analysis and Problem Complexity Artificial Intelligence Software Engineering Information Systems Applications (incl. Internet) Computer Communication Networks Management of Computing and Information Systems

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A reconfigurable Digital Signal processor using Residue Number System

A reconfigurable Digital Signal processor using Residue Numb...

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international conference on Information Science, Signal processing and their Applications

作者： Banerjee, Sharbari Sinha, Amitabha West Bengal University of Technology BF-142 Salt Lake City Kolkata-700064 India

ISBN: (纸本)9781424471676

Reconfigurable Computing has been evolving as a new platform for satisfying the simultaneous demand for application performance and flexibility placed over the present day DSP market. Since signal processing algorithms place significant demand on the processing power of the underlying platform, high performance reconfigurable architectures promise to be very efficient. the performance of traditional binary adders and multipliers for realizing Digital Signal processing (DSP) algorithms are often limited by the carry propagation delay. As a result, non-binary number systems such as, the Residue Number System (RNS) is becoming popular in the field of DSP because of its efficient performance in addition and multiplication operations. this paper presents a novel reconfigurable architecture using RNS for implementing DSP algorithms. the proposed architecture has been validated on Field Programmable Gate Array (FPGA). A Finite Impulse Response (FIR) filter has been implemented on the proposed reconfigurable processor and the synthesis results are presented. © 2010 IEEE.

关键词： Reconfigurable architectures

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Comparison of three parallel Point-Multiplication algorithms on Conic Curves

Comparison of Three Parallel Point-Multiplication Algorithms...

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Li, Yongnan Xiao, Limin Qin, Guangjun Li, Xiuqiao Lei, Songsong Beihang Univ State Key Lab Software Dev Environm Beijing 100191 Peoples R China

ISBN: (纸本)9783642246685

this paper makes a comparison of three parallel point-multiplication algorithms on conic curves over ring Zn. We propose one algorithm for paralleling point-multiplication by utilizing Chinese Remainder theorem to divide point-multiplication over ring Zn into two different point-multiplications over finite field and to compute them respectively. Time complexity and speedup ratio of this parallel algorithm are computed on the basis of our previous research about the basic parallel algorithms in conic curves cryptosystem. A quantitative performance analysis is made to compare this algorithm with two other algorithms we designed before. the performance comparison demonstrates that the algorithm presented in this paper can reduce time complexity of point-multiplication on conic curves over ring Zn and it is more efficient than the preceding ones.

关键词： conic curves ring Zn finite field Fp point-addition point-double point-multiplication Chinese Remainder theorem

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Scheduling of QR factorization algorithms on SMP and multi-core architectures

Scheduling of QR factorization algorithms on SMP and multi-c...

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16th Euromicro international conference on parallel, Distributed and Network-Based processing

作者： Quintana-Orti, Gregorio Quintana-Orti, Enrique S. Chan, Ernie de Geijn, Robert A. van Van Zee, Field G. Univ Jaume 1 Dept Ingn & Ciencia Computadores Castellon de La Plana 12071 Spain Univ Texas Austin Dept Comp Sci Austin TX 78712 USA

ISBN: (纸本)9780769530895

this paper examines the scalable parallel implementation of the QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-blocks are presented. Each implementation views a block of a matrix as the fundamental unit of data, and likewise, operations over these blocks as the primary unit of computation. the first is a conventional blocked algorithm similar to those included in libFLAME and LAPACK but expressed in a way that allows operations in the so-called critical path of execution to be computed as soon as their dependencies are satisfied. the second algorithm captures a higher degree of parallelism with an approach based on Givens rotations while preserving the performance benefits of algorithms based on blocked Householder transformations. We show that the implementation effort is greatly simplified by expressing the algorithms in code with the FLAME/FLASH API, which allows matrices stared by blocks to be viewed and managed as matrices of matrix blocks. the SuperMatrix run-time system utilizes FLASH to assemble and represent matrices but also provides out-of-order scheduling of operations that is transparent to the programmer Scalability of the solution is demonstrated on ccNUMA platform with 16 processors and an SMP architecture with 16 cores.

关键词： Matrix algebra

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thE SUPPORT FOR A DYNAMIC parallel OBJECT MODEL ON A TRANSPUTER-BASED ARCHITECTURE

THE SUPPORT FOR A DYNAMIC PARALLEL OBJECT MODEL ON A TRANSPU...

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10th ANNUAL international PHOENIX CONF ON COMPUTERS AND COMMUNICATIONS ( IPCCC 91 )

作者： CIAMPOLINI, A CORRADI, A LEONARDI, L Dipartimento di Elettronica Univ di Bologna Italy

ISBN: (纸本)0818621338

It is shown how a parallel object model can be used as a support environment for massively parallel architectures based on transputer technology. the intention is to verify that parallelism integrates well with such properties of the object paradigm as abstraction, uniformity, and dynamicity. the authors also present the guidelines to build prototypes by an approach based on primitives. In particular, the implemented primitives make possible the creation and communication of objects for a massively parallel architecture. Finally, trends in future work--static and dynamic allocation, replication and persistency of objects--are outlined.

关键词： MASSIVELY parallel architectures TRANSPUTER parallelISM OBJECTS

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A Customized processing-in-Memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. the design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

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