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Neural Network Data processing Technology Based on Deep Belief Networks 1

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10th international Scientific and Technical conference on Open Semantic Technologies for Intelligent System, OSTIS 2020

作者： Krasnoproshin, Viktor V. Matskevich, Vadim V. Faculty of Applied Mathematics and Computer Science Belarusian State University 4 Nezavisimost av. Minsk220030 Belarus

ISBN: (数字)9783030604479

ISBN: (纸本)9783030604462

the paper provides approach for building neural network data processing technology based on deep belief networks. A neural network architecture, focused on parallel data processing and an original training algorithm implementing the annealing method, is proposed. the approach effectiveness is demonstrated by solving the image compression problem as an example. © 2020, Springer Nature Switzerland AG.

关键词： Image compression

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HeAT - a Distributed and GPU-accelerated Tensor Framework for Data Analytics 8

HeAT - a Distributed and GPU-accelerated Tensor Framework fo...

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8th IEEE international conference on Big Data (Big Data)

作者： Goetz, Markus Debus, Charlotte Coquelin, Daniel Krajsek, Kai Comito, Claudia Knechtges, Philipp Hagemeier, Bjorn Tarnawa, Michael Hanselmann, Simon Siggel, Martin Basermann, Achim Streit, Achim German Aerosp Ctr Inst Software Technol SC Cologne Germany Forschungszentrum Julich Inst Rio & Geosci Agrosphere IBG 3 Julich Germany Forschungszentrum Julich FZJ Julich Supercomp Ctr JSC Julich Germany Karlsruhe Inst Technol KIT Steinbuch Ctr Comp SCC Karlsruhe Germany

ISBN: (纸本)9781728162515

To cope with the rapid growth in available data, the efficiency of data analysis and machine learning libraries has recently received increased attention. Although great advancements have been made in traditional array-based computations, most are limited by the resources available on a single computation node. Consequently, novel approaches must be made to exploit distributed resources, e.g. distributed memory architectures. To this end, we introduce IleAT, an array-based numerical programming framework for large-scale parallel processing with an easy-to-use NumPy-like API. HeAT utilizes PyTorch as a node-local eager execution engine and distributes the workload on arbitrarily large high-performance computing systems via MPI. It provides both low-level array computations, as well as assorted higher-level algorithms. With HeAT, it is possible for a NumPy user to take full advantage of their available resources, significantly I owering the bartier to distributed data analysis. When compared to similar frameworks, HeAT achieves speedups of up to two orders of magnitude.

关键词： IleAT Tensor Framework High-performance Computing PyTorch NumPy Message Passing Interface CPU Rig Data Analytics Machine Learning Dask Model parallelism parallel Application Frameworks

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A New Partially-parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio 33

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic L...

引用

33rd IEEE international conference on VLSI Design / 19th international conference on Embedded Systems

作者： Verma, Anuj Shrestha, Rahul Indian Inst Technol Mandi Sch Comp & Elect Engn Suran Himachal Prades India

ISBN: (数字)9781728157016

ISBN: (纸本)9781728157016

this paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. this architecture exploits the iterative decomposition of check node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. the proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10(-6) between 2 to 4 dB of bit-energy to noise-power-spectral density (E-b/N-o) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. the VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of-the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

关键词： Wireless communication LDPC code channel decoder layered min-sum decoding 5G new radio digital very-large-scale-integration (VLSI) architectures and field-programmable gate-array (FPGA)

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Constant-Weight Group Coded Bloom Filter for Multiple-Set Membership Queries 10th

Constant-Weight Group Coded Bloom Filter for Multiple-Set Me...

引用

10th international conference on Computer Engineering and Networks, CENet 2020

作者： Tian, Xiaomei Zhao, Huihuang College of Computer Science and Technology Hengyang Normal University Hengyang421002 China Hunan Provincial Key Laboratory of Intelligent Information Processing and Application Hengyang421002 China

ISBN: (纸本)9789811584619

Multiple-set membership query problem plays a very important role in many network systems, including packet forwarding architectures in big data centers, routing switching devices and internet firewall systems. Many solutions to multiple-set membership query problem are based on Bloom filters. And each of these solutions has its own merits. Some have high query speed and some have good accuracy. But generally, they cannot have both at the same time. In this paper, we propose a probabilistic data structure named constant-weight group coded Bloom Filter (CWGCBF) for fast and accurate multi-set membership query. the key technique in CWGCBF is encoding each elements set ID to constant weight code, and directly recording this constant-weight code in the bloom filter vector. Experimental results show that in terms of false positive ratio, CWGCBF, Shifting Bloom Filter and Combinatorial Bloom Filter have great advantages to the other compared Bloom filters, and in terms of time efficiency, CWGCBF and ID Bloom Filter are several times faster than the others. © 2021, the Editor(s) (if applicable) and the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Data structures

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Development of Text Data processing Pipeline for Scientific Systems 10th

Development of Text Data Processing Pipeline for Scientific ...

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10th Annual international conference on Biologically Inspired Cognitive architectures, BICA 2019

作者： Guseva, Anna I. Kuznetsov, Igor A. Bochkaryov, Pyotr V. Filippov, Stanislav A. Kireev, Vasiliy S. Kashirskoe shosse 31 Moscow115549 Russia

ISBN: (纸本)9783030257187

the aim of this work was to develop pipeline processing of scientific texts, including articles and abstracts, for their further categorization, identify patterns and build recommendations to users of scientific systems. the authors proposed a number of methods of pre-processing of texts, the method of cluster and classification analysis of texts, developed a software system of recommendations to users of scientific publications. To solve the problem of data preprocessing it is proposed to use parametrical approach to retrieve new – semantic – feature from textual publications – the type of scientific result. Scientific result type extraction is built just based on user’s need for content having specific property. To solve the problem of users’ profile clustering it is proposed to use ensemble method with distance metric change. For classification, ensemble method based on entropy is used. Evaluation of proposed methods and algorithms employment efficiency was carried out as applied to operation of search module of "Technologies in Education" international Congress of conferences information system. Author acknowledges support from the MEPhI Academic Excellence Project (Contract No. 02.a03.21.0005). © 2020, Springer Nature Switzerland AG.

关键词： Machine learning

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Building a lightweight container-based experimental platform for hpc education 10th

Building a lightweight container-based experimental platform...

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10th international Symposium on parallel architectures, algorithms and Programming, PAAP 2019

作者： Wang, Zelong Wu, Di Luo, Zhenxiao Du, Yunfei School of Data and Computer Science Sun Yat-sen University Guangzhou China Guangdong Key Laboratory of Big Data Analysis and Processing Guangzhou510006 China National Supercomputer Center in Guangzhou Guangzhou China

HPC (High Performance Computing) is of great significance due to its excellent performance in computing acceleration. However, unlike other techniques in computer science, learning HPC requires advanced computing resources such as large-scale clusters which directly increase the cost of study for students. To help students to learn HPC programming easily, we design and develop a lightweight container-based experimental platform to provide students with easily accessible and customizable HPC practice environments. In our platform, we integrate multiple practical functional modules for students, teachers, and administrators respectively. It is convenient for a user to access high-performance computing resources via a web portal, use highly customizable basic environments and have nice graphical hands-on interactive HPC learning experiences from our platform. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Containers

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ASIC Implementation of Fixed-Point Iterative, parallel, and Pipeline CORDIC Algorithm 8th

ASIC Implementation of Fixed-Point Iterative, Parallel, and ...

引用

8th international conference on Soft Computing for Problem Solving (SocProS)

作者： Jyothi, Grande Naga Debanjan, Kundu Anusha, Gorantla VIT Univ Vellore Tamil Nadu India GCT Coimbatore Coimbatore Tamil Nadu India

ISBN: (纸本)9789811500350;9789811500343

In this paper, we proposed a Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. the CORDIC is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point CORDIC algorithms are proposed. the standard CORDIC is also implemented for comparing the synthesis results. the proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard CORDIC. the ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. the standard and proposed CORDIC architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. the area and power consumption of the proposed CORDIC architecture are less when compared with standard CORDIC design.

关键词： CORDIC algorithm Pipeline parallel Digital signal processing

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Improving the performance of processing special computing tasks using an asynchronous actor model 10

Improving the performance of processing special computing ta...

引用

10th international conference on High-Performance Computing Systems and Technologies in Scientific Research, Automation of Control and Production, HPCST 2020

作者： Andrianova, E.G. Sachkov, V.E. Zhukov, D.O. MIREA Russian Technological University 78 Vernadsky Avenue Moscow119454 Russia

the use of third-party ready-made solutions to perform special computing tasks (SCT): processing text arrays in a natural language, the use of cryptography methods in data transmission networks, machine learning in solving applied problems, scientific computations and many other ones is a common practice in modern development of software systems. However, the use of third-party ready-made software solutions often leads to their poor optimization for parallel and distributed operation and to the difficulty in vertical and horizontal scaling, impossibility of modifying a solution, e.g., due to its legal protection, etc. In order to solve these problems, an asynchronous actor model can be used that facilitates developing software for processing special computing tasks. In addition, an asynchronous actor model allows parallel processing of input tasks, provides asynchronous operation, and extends its functionality to third-party ready-made solutions, that it is impossible or forbidden to modify to meet user's or optimization requirements. Methods, algorithms, and the entire logic of asynchronous actor operation involve transitions of actors from one state to another under the effect of input messages and returning the results of processed tasks to the frame system. this allows setting an automatic grammar and for using methods and approaches for developing software systems based on finite-state automata. the asynchronous actor operation scheme is represented by a directional state graph, which allows using the mathematical apparatus of the finite-state automaton theory (the Mealy model) to describe the same. the developed model is convenient for designing and organizing the SCT processing using computer systems. the use of the asynchronous actor model makes it possible, in special operation modes, to increase the performance of poorly optimized SCT without modifying the same, as compared to task processing without using the asynchronous actor model. © Published under li

关键词： Computer software

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PPBT: A High Performance parallel Search Tree

PPBT: A High Performance Parallel Search Tree

引用

international conference on High Performance Computing

作者： Jiawen Guan Rui Fan ShanghaiTech University Shanghai China

ISBN: (纸本)9781665410175

Search trees are one of the most important and widely used data structures, and parallelization is an effective method to improve their performance. However, many existing parallel search trees incur high synchronization costs and low memory I/O efficiency, which limits their performance. We propose PPBT, a batched parallel search tree which minimizes synchronization by partitioning the tree using novel algorithms and minimizing I/O cost using buffering. We give a new sequential algorithm for batch processing on search trees with optimal I/O efficiency for insert and delete operations, and also present a fast parallel algorithm for joining disjoint search trees. We show experimentally that PPBT is over 6×faster than the state-of-the-art parallel tree in [1] and over 40× faster than the concurrent search tree in [7], and achieves 21×speedup using 32 threads. PPBT's throughput on searches is lower due to reduced opportunities for buffering, but is still 1.3 × that of [1]. In addition, PPBT has good response times for searches, for example completing 100K searches in under 1 ms in a tree with 10M elements.

关键词： Costs Scalability Instruction sets High performance computing Memory management throughput Partitioning algorithms

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GPU Accelerated Matrix Factorization for Recommender Systems

GPU Accelerated Matrix Factorization for Recommender Systems

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IEEE international conference on Big Data Analysis (ICBDA)

作者： Doruk Kilitcioglu Nicholas Greenquist Mohamed Zahran Anasse Bari Courant Institute of Mathematical Sciences New York University USA

Matrix Factorization (MF) is a popular algorithm used to power many recommender systems. Efficient and scalable MF algorithms are essential in order to train on the massive datasets that large scale recommender systems utilize. Graphics processing Unit (GPU) technology has become very popular in recent years and has become widely used in machine learning. the massive parallelism GPUs offer creates an opportunity to develop an accelerated MF algorithm. this paper presents cu2rec, a matrix factorization algorithm written in CUDA. cu2rec implements a parallel version of Stochastic Gradient Descent (SGD) to solve large scale MF problems. cu2rec utilizes multiple advanced techniques to harness better performance from a GPU. these include aggressive use of constant memory for hyper-parameters and registers for heavily reused values, a sparse matrix data structure, a reduction sum total loss kernel, a novel approach to parallel lock-free updating of feature weights with minimized global memory writes, and fairness across weight updates using user index striding. With a single NVIDIA GPU, cu2rec can be 10x faster than state of the art sequential algorithms while reaching similar error metrics.

关键词： Measurement Machine learning algorithms Graphics processing units Stochastic processes Machine learning Big Data Acceleration

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