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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2803 条记录，以下是401-410 订阅

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AttenFace: A Real Time Attendance System Using Face Recognition

AttenFace: A Real Time Attendance System Using Face Recognit...

引用

conference on Information and Communication Technology (CICT)

作者： Ashwin Rao International Institute of Information Technology Hyderabad Hyderabad India

ISBN: (数字)9781665473125

ISBN: (纸本)9781665473132

the current approach to marking attendance in colleges is tedious and time consuming. I propose AttenFace, a standalone system to analyze, track and grant attendance in real time using face recognition. Using snapshots of class from live camera feed, the system identifies students and marks them as present in a class based on their presence in multiple snapshots taken throughout the class duration. Face recognition for each class is performed independently and in parallel, ensuring that the system scales with number of concurrent classes. Further, the separation of the face recognition server from the back-end server for attendance calculation allows the face recognition module to be integrated with existing attendance tracking software like Moodle. the face recognition algorithm runs at 10 minute intervals on classroom snapshots, significantly reducing computation compared to direct processing of live camera feed. this method also provides students the flexibility to leave class for a short duration (such as for a phone call) without losing attendance for that class. Attendance is granted to a student if he remains in class for a number of snapshots above a certain threshold. the system is fully automatic and requires no professor intervention or any form of manual attendance or even camera set-up, since the back-end directly interfaces with in-class cameras. AttenFace is a first-of-its-kind one-stop solution for face-recognition-enabled attendance in educational institutions that prevents proxy, handling all aspects from students checking attendance to professors deciding their own attendance policy, to college administration enforcing default attendance rules.

关键词： Face recognition Software algorithms Manuals Cameras Real-time systems Software Information and communication technology

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Vectorized Character Counting for Faster Pattern Matching 10

Vectorized Character Counting for Faster Pattern Matching

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12th international Joint conference on Biomedical Engineering Systems and Technologies / 10th international conference on Bioinformatics Models, Methods and algorithms (BIOINFORMATICS)

作者： Snytsar, Roman Microsoft Res One Microsoft Way Redmond WA 98052 USA

ISBN: (纸本)9789897583537

Many modern sequence alignment tools implement fast string matching using the space efficient data structure called a FM-index. the succinct nature of this data structure presents unique challenges for the algorithm designers. In this paper, we explore the opportunities for parallelization of the exact and inexact matches, and present an efficient solution for the Occ portion of the algorithm that utilizes the instruction-level parallelism of the modern CPUs. Our implementation computes all eight Occ values required for the inexact match algorithm step in a single pass. We showcase the algorithm performance in a multi-core genome aligner and discuss effects of the memory prefetch.

关键词： parallel processing Vectorization Bioinformatics FM-Index

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Neural Architecture Search Based on Tabu Search and Evolutionary Algorithm

Neural Architecture Search Based on Tabu Search and Evolutio...

引用

IEEE international conference on Cyber Technology in Automation, Control, and Intelligent Systems

作者： Zhun Fan Zhoubin Long Wenji Li Zhaojun Wang Zhi Yang Liu Wang Guangdong Province Engineering college Shantou University Shantou Guangdong China

Most existing optimization methods for neural architecture search (NAS), including evolutionary algorithms, reinforcement learning and gradient-based approaches, have not employed memory strategies explicitly, which may lack of efficiency when searching neural architectures. To solve this issue, we propose a new NAS approach by using an evolutionary algorithm which employs a tabu mechanism to help to improve the search efficiency. To be more specific, the individuals of parent population are selected by tournament selection and tabu list. the tournament selection select parent population according to the accuracy of each individual. And the tabu mechanism builds a tabu list to record the chosen operations in the last previous search process, which employs a search memory mechanism to improve the efficiency explicitly. To confirm the superior performance of our approach, a well-designed surrogate model is used to accelerate the process of performance evaluation on CIFAR-10. the comprehensive experimental results show that the proposed method can reach to 2.48% error rate with about 2 GPU days, which demonstrates the superiority of the suggested method.

关键词： Performance evaluation Error analysis Sociology Memory management Graphics processing units Optimization methods Evolutionary computation

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parallelization of Data Buffering and processing Mechanism in Mesh Wireless Sensor Network for IoT Applications 6th

Parallelization of Data Buffering and Processing Mechanism i...

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6th international conference on Advanced Computing, Networking, and Informatics, ICACNI 2018

作者： Jain, Monika Saxena, Rahul Jaidka, Siddharth Jhamb, Mayank Kumar School of Computing and Information Technology Manipal University Jaipur Jaipur India

ISBN: (纸本)9789811396793

IoT, being a field of great interest and importance for the coming generations, involves certain challenging and improving aspects for the IoT application developers and researchers to work upon. A wireless sensor mesh networking has emerged as an attractive option for wide range of low-power IoT applications. this paper shows that how the data can be stored, read and processed parallelly by the parent node in the cluster from multiple sensor nodes, thus reducing the response time drastically. the use of parallelized algorithm for the communication protocol optimized using OpenMP standards for multi-core architecture between the sensors and parent node enables multiple radio technologies to be used for an application which could not be more than one in case of serial processing. the proposed algorithm has been tested for a wireless network application measuring temperature and moisture concentrations using numerous sensors for which the response time is recorded to be less than 10 ms. the paper also discusses in detail the hardware configurations for the application tested along with the results throwing light on the parallel mechanism for buffering and processing the messages. Finally, the paper is concluded by claiming the edge of parallel algorithm-based routing protocol over the serial in the light of graphical results and analysis. © 2020, Springer Nature Singapore Pte Ltd.

关键词： parallel algorithms

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Parameter prediction for unseen deep architectures 21

Parameter prediction for unseen deep architectures

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Proceedings of the 35th international conference on Neural Information processing Systems

作者： Boris Knyazev Michal Drozdzal Graham W. Taylor Adriana Romero-Soriano University of Guelph and Vector Institute for Artificial Intelligence Facebook AI Research University of Guelph and Vector Institute for Artificial Intelligence and Canada CIFAR AI Chair Facebook AI Research and McGill University

ISBN: (纸本)9781713845393

Deep learning has been successful in automating the design of features in machine learning pipelines. However, the algorithms optimizing neural network parameters remain largely hand-designed and computationally inefficient. We study if we can use deep learning to directly predict these parameters by exploiting the past knowledge of training other networks. We introduce a large-scale dataset of diverse computational graphs of neural architectures – DEEPNETS-1M– and use it to explore parameter prediction on CIFAR-10 and ImageNet. By leveraging advances in graph neural networks, we propose a hypernetwork that can predict performant parameters in a single forward pass taking a fraction of a second, even on a CPU. the proposed model achieves surprisingly good performance on unseen and diverse networks. For example, it is able to predict all 24 million parameters of a ResNet-50 achieving a 60% accuracy on CIFAR-10. On ImageNet, top-5 accuracy of some of our networks approaches 50%. Our task along with the model and results can potentially lead to a new, more computationally efficient paradigm of training networks. Our model also learns a strong representation of neural architectures enabling their analysis.

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A 2D parallel Triangle Counting Algorithm for Distributed-Memory architectures 19

A 2D Parallel Triangle Counting Algorithm for Distributed-Me...

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48th international conference on parallel processing (ICPP)

作者： Tom, Ancy Sarah Karypis, George Univ Minnesota Dept Comp Sci & Engn Minneapolis MN 55455 USA

ISBN: (纸本)9781450362955

Triangle counting is a fundamental graph analytic operation that is used extensively in network science and graph mining. As the size of the graphs that needs to be analyzed continues to grow, there is a requirement in developing scalable algorithms for distributed-memory parallel systems. To this end, we present a distributedmemory triangle counting algorithm, which uses a 2D cyclic decomposition to balance the computations and reduce the communication overheads. the algorithm structures its communication and computational steps such that it reduces its memory overhead and includes key optimizations that leverage the sparsity of the graph and the way the computations are structured. Experiments on synthetic and real-world graphs show that our algorithm obtains an average relative speedup range between 3.24 to 7.22 out of 10.56 across the datasets using 169 MPI ranks over the performance achieved by 16 MPI ranks. Moreover, we obtain an average speedup of 10.2 times on comparison with previously developed distributed-memory parallel algorithms.

关键词： triangle counting graph analytics distributed-memory

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Series-parallel Differential Power processing Scheme for Maximised Power Extraction from Mismatched Photovoltaic Panels

Series-Parallel Differential Power Processing Scheme for Max...

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the 10th international conference on Power Electronics, Machines and Drives (PEMD 2020)

作者： M. Etarhouni B. Chong L. Zhang School of Electronic & Electrical Engineering University of Leeds Leeds UK

In recent years, there has been an increasing interest in utilising Differential Power processing converters (DPP) in Photovoltaic (PV) applications to achieve the maximum power point tracking (MPPT), minimum losses and high efficiency under unequal lighting conditions. this paper presents a novel Series and parallel (SP) DPP converters scheme, with a proper control technique to optimise the system output power under mismatch conditions compared to that of a conventional 2×2 SP array which is protected with bypass diodes. the simulation results of such system show significant improvements in the total power of the SP-DPP system under PSCs.

关键词： photovoltaic power systems diodes solar cell arrays maximum power point trackers

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Architecture for parallel PV Strings using the Switched-Capacitor-Based Differential Power processing Techniqu

Architecture for Parallel PV Strings using the Switched-Capa...

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the 10th international conference on Power Electronics, Machines and Drives (PEMD 2020)

作者： K. A. K Niazi Y. Yang D. Sera Department of Energy Technology Aalborg University Pontoppidanstraede 101 Aalborg Denmark

Mismatch effects are common in photovoltaic (PV) systems, which affect the overall system performance and the PV module life. A mismatch causes an imbalance in the PV module voltages, and therefore, it is not recommended to connect PV modules in parallel due to increased power losses and stresses. To mitigate the effect of mismatch, module-level power electronics converters are considered as an effective solution. Accordingly, this paper introduces a differential power processing (DPP) converter based on switched-capacitors (SCs) for parallel-connected PV strings. the proposed DPP converters are connected across each PV module, which equalizes the PV module voltages. the technique can help to generate more output power regardless of mismatch between PV modules and make the parallelization of PV strings possible. the proposed architecture is analyzed through simulations and compared with parallel-connected PV strings using Schottky diodes.

关键词： Schottky diodes maximum power point trackers photovoltaic power systems

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Proceedings of the 10th international Workshop on Programming Models and Applications for Multicores and Manycores, PMAM 2019

Proceedings of the 10th International Workshop on Programmin...

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10th international Workshop on Programming Models and Applications for Multicores and Manycores, PMAM 2019

ISBN: (纸本)9781450362900

the proceedings contain 10 papers. the topics discussed include: LiTM: a lightweight deterministic software transactional memory system;don’t forget about synchronization! a case study of K-means on GPU;Gecko: hierarchical distributed view of heterogeneous shared memory architectures;brie: a specialized Trie for concurrent datalog;wait-free dynamic transactions for linked data structures;deciphering predictive schedulers for heterogeneous-ISA multicore architectures;formal verification through combinatorial topology: the CAS-extended model;process barrier for predictable and repeatable concurrent execution;libMPNode: an OpenMP runtime for parallel processing across incoherent domains;and task-DAG support in single-source PHAST library: enabling flexible assignment of tasks to CPUs and GPUs in heterogeneous architectures.

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Scalable and Parameterizable Processor Array Architecture for Similarity Distance Computation 10

Scalable and Parameterizable Processor Array Architecture fo...

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10th international conference on Information and Communication Systems (ICICS)

作者： Kanan, Awos Gebali, Fayez Ibrahim, Atef Li, Kin Fun Princess Sumaya Univ Technol Dept Comp Engn Amman Jordan Univ Victoria Dept Elect & Comp Engn Victoria BC Canada Prince Sattam Bin AbdulAziz Univ Dept Comp Engn Al Kharj Saudi Arabia

ISBN: (纸本)9781728100456

Processorarray architecture is a popular approach to improve computation of similarity distance matrices;however, most of the proposed architectures are designed in an ad hoc manner, some have not even considered dimensionality and size of the datasets. We believe a systematic approach is necessary to explore the design space. In this work, we present a technique for designing scalable processor array architecture for the similarity distance matrix computation. Implementation results of the proposed architecture show improved compromise between area and speed. Moreover, it scales better for large and high-dimensional datasets since the architecture is fully parameterized and only has to deal with one data dimension in each time step.

关键词： Processor arrays scalable hardware similarity measures parallel computing

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