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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Successive-parallel Interference Cancellation Multi-user Detection Algorithm for MUSA Uplink 10th

Successive-Parallel Interference Cancellation Multi-user Det...

引用

10th European-Alliance-for-Innovation (EAI) international conference on Wireless and Satellite Systems (WiSATS)

作者： Wu, Shaochuan Zuo, Rundong Zhang, Wenbing Song, Yanwu Harbin Inst Technol Sch Elect & Informat Engn Harbin Peoples R China

ISBN: (纸本)9783030191566;9783030191559

With the approaching of Internet of things (IoT), non-orthogonal multiple access technology was proposed in the fifth generation (5G) mobile communication system to improve the system capacity and meet the needs of massive connectivity. Multi-User Shared Access (MUSA) technology is a non-orthogonal multiple access technology of code domain. MUSA receiver adopts multi-user detection algorithm, mainly using interference cancellation based on linear detection. this paper proposes the successive-parallel interference cancellation multi-user detection algorithm for the shortage of typical multi-user detection algorithms of MUSA uplink receiver, and gives the comparison results of the proposed algorithm and typical algorithms. Compared with parallel interference cancellation detection algorithm, the proposed algorithm improves the detection performance greatly. Compared with successive interference cancellation detection algorithm, the proposed algorithm reduces the processing time delay effectively.

关键词： Multi-User Shared Access Multi-user detection Interference cancellation Time delay

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the Impact of GPU DVFS on the Energy and Performance of Deep Learning: an Empirical Study 19

The Impact of GPU DVFS on the Energy and Performance of Deep...

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10th ACM international conference on Future Energy Systems (e-Energy)

作者： Tang, Zhenheng Wang, Yuxin Wang, Qiang Chu, Xiaowen Hong Kong Baptist Univ Dept Comp Sci Hong Kong Peoples R China

ISBN: (纸本)9781450366717

Over the past years, great progress has been made in improving the computing power of general-purpose graphics processing units (GPGPUs), which facilitates the prosperity of deep neural networks (DNNs) in multiple fields like computer vision and natural language processing. A typical DNN training process repeatedly updates tens of millions of parameters, which not only requires huge computing resources but also consumes significant energy. In order to train DNNs in a more energy-efficient way, we empirically investigate the impact of GPU Dynamic Voltage and Frequency Scaling (DVFS) on the energy consumption and performance of deep learning. Our experiments cover a wide range of GPU architectures, DVFS settings, and DNN configurations. We observe that, compared to the default core frequency settings of three tested GPUs, the optimal core frequency can help conserve 8.7%similar to 23.1% energy consumption for different DNN training cases. Regarding the inference, the benefits vary from 19.6%similar to 26.4%. Our findings suggest that GPU DVFS has great potentials to help develop energy efficient DNN training/inference schemes.

关键词： Graphics processing Units Dynamic Voltage and Frequency Scaling Deep Convolutional Neural Network

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An Image thresholding Method Based on Differential Evolution Algorithm and Genetic Algorithm 10

An Image Thresholding Method Based on Differential Evolution...

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10th IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and Applications (IDAACS)

作者： Ye, Zhiwei Zhang, Aixin Cao, Ye Ma, Lie Jin, Can Hu, Xiang Hu, Jiwei Hubei Univ Technol Wuhan Hubei Peoples R China Wuhan Jizhi Technol Co LTD Wuhan Hubei Peoples R China Wuhan Fiberhome Tech Serv Co Ltd Wuhan 430074 Hubei Peoples R China

ISBN: (纸本)9781728140681

thresholding is the simplest but most effecttive segmentation technique for image analysis. However, the computational complexity increases exponentially with the increase of threshold number in order to seek the most appropriate threshold values. therefore, stochastic optimization algorithm are often used to overcome excessive computational problems, but the single optimization algorithm often falls into the local optimum. In general, hybrid algorithm is able to produce better performance. As a result, a parallel coupled mode(DE_GA in brief) of differential evolution algorithm (DE) and genetic algorithm (GA) is proposed for solving multi-threshold problem and the maximum variance is used as the fitness function. the experimental result displays that compared with a single algorithm, the results of the hybrid algorithm are relatively stable, which means that the parallel coupled DE_GA algorithm combined with Otsu might be an effect and practical image segmentation method.

关键词： parallel coupled mode Genetic algorithms Differential Evolution Algorithm Image segmentation, thresholding

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DASH: Dynamic Scheduling Algorithm for Single-ISA Heterogeneous Nano-scale Many-Cores

DASH: Dynamic Scheduling Algorithm for Single-ISA Heterogene...

引用

international econference on Computer and Knowledge Engineering (ICCKE)

作者： Keihaneh Kia Amir Rajabzadeh Engineering faculty Razi University Kermanshah Iran

ISBN: (数字)9781728185668

ISBN: (纸本)9781728185675

the difference in the performance of identical cores due to the process variation and the different distance of cores from the shared last level cache (LLC) besides power limitation should be considered in scheduling algorithms to exploit the maximum performance of the Nano-scale many-core processors. this paper presents a dynamic heuristic scheduling algorithm, called DASH, to maximize performance under the mentioned challenges. In this regard, we estimate the execution time of each task of a job on a core as a relation of frequency and the communication cost of the core, as well as the type of the job and its tasks. According to this estimation model DASH selects some cores to maximize performance while exploiting DVFS to reduce the effect of power limitation. the time overhead of our algorithm is compatible with dynamic systems. We evaluate DASH by running random sequences of jobs from SPLASH parallel benchmark suite in Sniper and MACPat simulator for performance and power estimation. the results show that the throughput of DASH is 7.1% and 30.4% more than two similar algorithms.

关键词： Program processors Task analysis Multicore processing Heuristic algorithms Scheduling algorithms Estimation Dynamic scheduling

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10th TPC Technology conference on Performance Evaluation and Benchmarking, TPCTC 2018, held in conjunction with 44th international conference on Very Large Data Bases, VLDB 2018

10th TPC Technology Conference on Performance Evaluation and...

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10th TPC Technology conference on Performance Evaluation and Benchmarking, TPCTC 2018, held in conjunction with 44th international conference on Very Large Data Bases, VLDB 2018

ISBN: (纸本)9783030114039

the proceedings contain 11 papers. the special focus in this conference is on Performance Evaluation and Benchmarking. the topics include: Lessons learned from the industry’s first TPC benchmark DS (TPC-DS);uniBench: A benchmark for multi-model database management systems;polyBench: the first benchmark for polystores;benchmarking distributed data processing systems for machine learning workloads;Characterizing the performance and resilience of HCI clusters with the TPCx-HCI benchmark;Requirements for an enterprise AI benchmark;towards evaluation of tensorflow performance in a distributed compute environment;A comparison of two cache augmented SQL architectures;benchmarking and performance analysis of event sequence queries on relational database.

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High-Performance architectures for Finite Field Inversion over GF(2¹⁶³) 10

High-Performance Architectures for Finite Field Inversion ov...

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10th Southern conference on Programmable Logic (SPL)

作者： Realpe-Munoz, Paulo David-Nunez, Guillermo Velasco-Medina, Jaime Inst Univ Antonio Jose Camacho Inteligo Res Grp Cali Colombia Univ Valle Bionanoelect Res Grp Cali Colombia

ISBN: (纸本)9781728113630

Inversion is the most computationally expensive finite field operation in public-key cryptographic such as elliptic curve cryptography (ECC). this paper presents high- performance architectures for performing the finite field inversion using Gaussian Normal Bases (GNB) and a digit-level serial-in parallel-out multiplier (DL-SIPO) over GF (2(163)). We propose three architectures to carry out the inversion operation. the first one is based on classic Itoh-Tsujji Algorithm (ITA), the second one carries out the inversion operation according to the NIST binary fields over GF (2(163)) and finally, the last one is based on Fermat's Little theorem (FLT). the architectures were designed using VHDL description, synthesized on the Stratix IV FPGA using Quartus Prime 17.0, and verified in ModelSim and Matlab. the synthesis results show that the designed architectures present a very good performance using low area. In this case, the processing time and area resources to compute the inversion operation were 114.2, 115.9 and 114.5 ns using 11624, 11558 and 11690 LUTs, respectively.

关键词： Finite field inversion Multiplier Hardware architectures Normal Bases Elliptic Curve Cryptosystems

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13th international conference on High Performance Computing in Computational Science, VECPAR 2018

13th International Conference on High Performance Computing ...

引用

13th international conference on High Performance Computing in Computational Science, VECPAR 2018

ISBN: (纸本)9783030159955

the proceedings contain 18 papers. the special focus in this conference is on High Performance Computing in Computational Science. the topics include: A Scheduling theory Framework for GPU Tasks Efficient Execution;A Timer-Augmented Cost Function for Load Balanced DSMC;Accelerating Scientific Applications on Heterogeneous Systems with HybridOMP;a New parallel Benchmark for Performance Evaluation and Energy Consumption;bigger Buffer k-d Trees on Multi-Many-Core Systems;a parallel Generator of Non-Hermitian Matrices Computed from Given Spectra;LRMalloc: A Modern and Competitive Lock-Free Dynamic Memory Allocator;towards a Strategy for Performance Prediction on Heterogeneous architectures;Dynamic Configuration of CUDA Runtime Variables for CDP-Based Divide-and-Conquer algorithms;Design, Implementation and Performance Analysis of a CFD Task-Based Application for Heterogeneous CPU/GPU Resources;Optimizing Packed String Matching on AVX2 Platform;A GPU-Based Metaheuristic for Workflow Scheduling on Clouds;a Systematic Mapping on High-Performance Computing for Protein Structure Prediction;performance Evaluation of Deep Learning Frameworks over Different architectures;non-uniform Domain Decomposition for Heterogeneous Accelerated processing Units;performance Evaluation of Two Load Balancing algorithms for Hybrid Clusters.

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Approximate Sorting Check Node processing in Non-Binary LDPC Decoders

Approximate Sorting Check Node Processing in Non-Binary LDPC...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Dimitris Chytas Vassilis Paliouras University of Patras Patras Greece

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

this paper proposes the use of parallel approximate sorting networks in Non-Binary LDPC decoders and quantifies their impact in terms of performance and complexity. Motivated by the messages truncation concept of the Extended Min Sum (EMS) algorithm and the reduction it induces on the decoding complexity, we seek for an approximate parallel sorting strategy for the Elementary Check Node (ECN) Unit processing in the EMS algorithm. We quantify the impact of parallel approximate sorting on both error correction decoding performance and hardware complexity. Bubble check sorting methods are compared to proposed parallel approximate sorting techniques in terms of BER vs. noise plots. Furthermore hardware synthesis results are provided to demonstrate the effects of parallel sorting networks on area and throughput. In certain cases of practical interest, a modest degradation of 0.2 dB in coding gain is imposed; however due to proposed parallel approximate sorters, the latency of ECN can be reduced by up to a factor of two or be logarithmic to the input sequence length, in certain architectures. To better illustrate the impact of the proposed techniques, a complete NB-LDPC decoder has been implemented and used for evaluation; it is found that a substantial reduction in the number of clock cycles required per decoding iteration is achieved by the proposed techniques, more than 50% in certain cases.

关键词： Sorting Decoding Complexity theory Parity check codes Approximation algorithms Degradation Signal to noise ratio

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Multiple algorithms Against Multiple Hardware architectures: Data-Driven Exploration on Deep Convolution Neural Network 16th

Multiple Algorithms Against Multiple Hardware Architectures:...

引用

16th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2019

作者： Xu, Chongyang Luan, Zhongzhi Gao, Lan Wang, Rui Zhang, Han Zhang, Lianyi Liu, Yi Qian, Depei Beihang University Beijing China Science and Technology on Special System Simulation Laboratory Beijing Simulation Center Beijing China

ISBN: (纸本)9783030307080

With the rapid development of deep learning (DL), various convolution neural network (CNN) models have been developed. Moreover, to execute different DL workloads efficiently, many accelerators have been proposed. To guide the design of both CNN models and hardware architectures for a high-performance inference system, we choose five types of CNN models and test them on six processors and measure three metrics. With our experiments, we get two observations and conduct two insights for the design of CNN algorithms and hardware architectures. © 2019, IFIP international Federation for Information processing.

关键词： Neural network models

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Hardware Deceleration of Kvazaar HEVC Encoder 19th

Hardware Deceleration of Kvazaar HEVC Encoder

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19th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation (SAMOS)

作者： Sainio, Joose Mercat, Alexandre Vanne, Jarno Tampere Univ Tampere Finland

ISBN: (纸本)9783030275624;9783030275617

High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding (AVC) standard but tackling its huge complexity calls for efficient HEVC codec implementations. the recent advances in Graphics processing Units (GPUs) have made programmable general-purpose GPUs (GPGPUs) a popular option for accelerating various video coding tools. Massively parallel GPU architectures are particularly well suited for hardware-oriented full search (FS) algorithm in HEVC integer motion estimation (IME). this paper analyzes the feasibility of a GPU-accelerated FS implementation in the practical Kvazaar open-source HEVC encoder. According to our evaluations, implementing FS on AMD Radeon RX 480 GPU makes Kvazaar 12.5 times as fast as the respective anchor implemented entirely on an Intel 8-core i7 processor. However, the obtained speed gain is lost when fast IME algorithms are put into use in the anchor. For example, executing the anchor with hexagon-based search (HEXBS) algorithm is almost two times as fast as our GPU-accelerated proposal and the benefit of GPU offloading is reduced to a slight coding gain of 1.2%. Our results show that accelerating IME on a GPU speeds up non-practical encoders due to their enormous inherent complexity but the price paid with practical encoders tends to be too high. Conditional processing schemes of fast IME algorithms can be efficiently executed on processors without any substantial coding loss over that of FS. Nevertheless, we still believe there might be room for exploiting GPU on IME acceleration but GPU-parallelized fast algorithms are needed to get value for additional implementation cost and power budget.

关键词： High Efficiency Video Coding (HEVC) HEVC encoder Graphics processing Unit (GPU) Integer Motion Estimation (IME) Full-Search (FS)

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