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10th international conference on Supercomputing, ISUM 2019

作者： Gutiérrez-Garibay, Daniel Híjar, Humberto Engineering School La Salle University Mexico Benjamin Franklin 45 Mexico City06140 Mexico

ISBN: (纸本)9783030380427

Molecular rotors are microscopic structures composed of two coupled parts that can rotate mutually. they have promising applications in viscosity measurement and flow detection in micro-sized and complex geometries. We propose a model for studying molecular rotors as classical systems moving in viscous environments, subjected to internal interactions and stochastic forces. Our model is expressed as a set of non-linear stochastic Langevin equations that are solved numerically using a Brownian Dynamics procedure. Attention is focused on the calculation of the two-time correlation function of the internal angular variable. For small internal forces, this correlation turns out to have a very slow time decay and its correct estimation requires long numerical experiments. We propose a CUDA implementation for a computer cluster with TESLA GPUs that calculates angular correlation functions in parallel. the implementation reduces the used computational time considerably in comparison with the one consumed by a usual serial scheme. It allows for the simulation of massive molecular rotors ensembles from which reliable results can be obtained. It is discussed how the GPU implementation can be improved in modern GPUs architectures. © Springer Nature Switzerland AG 2019.

关键词： Graphics processing unit

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eMDPM: Efficient Multidimensional Pattern Matching Algorithm for GPU 2nd

eMDPM: Efficient Multidimensional Pattern Matching Algorithm...

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2nd international conference on Smart Innovations in Communications and Computational Sciences ICSICCS-2018

作者： Raj, Supragya Chodnekar, Siddha Prabhu Harish, T. Sriraman, Harini School of Computing Science and Engineering Vellore Institute of Technology Chennai Campus Chennai600127 India

ISBN: (纸本)9789811324130

parallelizing pattern matching in multidimensional images is very vital in many applications to improve the performance. With SIMT architectures, the performance can be greatly enhanced if the hardware threads are utilized to the maximum. In the case of pattern matching algorithms, the main bottleneck arises due to the reduction operation that needs to be performed on the multiple parallel search operations. this can be solved by using Shift-Or operations. the recent trend has shown the improvement in pattern matching using Shift-Or operations for bit pattern matching. this has to be extended for multiple dimensional images like hyper-cubes. In this paper, we have extended the Shift-Or pattern matching for multidimensional images. the algorithm is implemented for GPU architectures. the complexity of the proposed algorithm is $$ m*\frac{log(n)}{kw} $$ where m is the number of dimensions, n is the size of the array if the multidimensional matrix values are placed in a single dimensional array, k is the size of the pattern and w is the size of the tile. From the result analysis it is found that the performance is maximum, when the pattern size matches the tile size and it is less than 64. this restriction is due to the size of the warp considered. © 2019, Springer Nature Singapore Pte Ltd.

关键词： Graphics processing unit

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A FPGA-based accelerator implementaion for YOLOv2 object detection using Winograd algorithm

A FPGA-based accelerator implementaion for YOLOv2 object det...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Peng Lv Wei Liu Jinghui Li School of Computer Engineering and Science Shanghai University Shanghai China

ISBN: (纸本)9781665423144;9781665446235

Convolutional neural networks (CNNs) are used in many computer vision applications and the computational complexity of CNN has increased greatly. Since CPUs can hardly provide the massive parallelism required by CNNs, many hardware accelerators, such as GPU, FPGA, and ASIC, have been developed to improve the performance of CNNs. Of these designs, FPGA-based accelerators have become a special option due to their advantages of high flexibility, low power consumption and extensive DSP resources. In this paper, an OpenCL-based CNN accelerator is designed for FPGA and a variety of model compression techniques are applied to the YOLOv2 model. the accelerator uses the Winograd algorithm to implement convolution efficiently and reduce the number of multiplications by 38% to 60% for YOLOv2 model, also this design makes full use of the available memory access bandwidth and DSP resources. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results on YOLOv2 network show a 1.2x~1.9x speedup compared with im2col convolution algorithms and the performance of our FPGA design can reach 10ms per image in terms of latency, compared to 16ms per image with Nvidia Tesla V100 GPU.

关键词： Power demand Convolution Memory management Graphics processing units Random access memory Object detection parallel processing

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Captioning Ultrasound Images Automatically 22nd

Captioning Ultrasound Images Automatically

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10th international Workshop on Machine Learning in Medical Imaging (MLMI) / 22nd international conference on Medical Image Computing and Computer-Assisted Intervention (MICCAI)

作者： Alsharid, Mohammad Sharma, Harshita Drukker, Lior Chatelain, Pierre Papageorghiou, Aris T. Noble, J. Alison Univ Oxford Inst Biomed Engn Oxford England Univ Oxford Nuffield Dept Womens & Reprod Hlth Oxford England

ISBN: (纸本)9783030322519;9783030322502

We describe an automatic natural language processing (NLP)-based image captioning method to describe fetal ultrasound video content by modelling the vocabulary commonly used by sonographers and sonologists. the generated captions are similar to the words spoken by a sonographer when describing the scan experience in terms of visual content and performed scanning actions. Using full-length second-trimester fetal ultrasound videos and text derived from accompanying expert voice-over audio recordings, we train deep learning models consisting of convolutional neural networks and recurrent neural networks in merged configurations to generate captions for ultrasound video frames. We evaluate different model architectures using established general metrics (BLEU, ROUGE-L) and application-specific metrics. Results show that the proposed models can learn joint representations of image and text to generate relevant and descriptive captions for anatomies, such as the spine, the abdomen, the heart, and the head, in clinical fetal ultrasound scans.

关键词： Image description Image captioning Deep learning Natural language processing Recurrent neural networks Fetal ultrasound

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Efficient parallel sort on AVX-512-based multi-core and many-core architectures 21

Efficient parallel sort on AVX-512-based multi-core and many...

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21st IEEE international conference on High Performance Computing and Communications, 17th IEEE international conference on Smart City and 5th IEEE international conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Yin, Zekun Zhang, Tianyu Muller, Andre Liu, Hui Wei, Yanjie Schmidt, Bertil Liu, Weiguo School of Software Shandong University Jinan China Shenzhen Research Institute Shandong University China Institute for Computer Science Johannes Gutenberg University Mainz Germany Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen China National Supercomputing Center in Wuxi Wuxi China

ISBN: (纸本)9781728120584

Sorting kernels are a fundamental part of numerous applications. the performance of sorting implementations is usually limited by a variety of factors such as computing power, memory bandwidth, and branch mispredictions. In this paper we propose an efficient hybrid sorting method which takes advantage of wide vector registers and the high bandwidth memory of modern AVX-512-based multi-core and many-core processors. Our approach employs a combination of vectorized bitonic sorting and load-balanced multi-threaded merging. thread-level and data-level parallelism are used to exploit both compute power and memory bandwidth. Our single-threaded implementation is ~30x faster than qsort in the C standard library and ~10x faster than C++'s std::sort. Compared with the Intel Performance Primitives (IPP) library which is one of the most efficient CPU-based radix sort implementation, we obtain a speedup of 1.3 to 2.6. Furthermore, we achieve a peak performance of sorting 1.14 billion floats per second on a Xeon Phi 7210 processor. Moreover, we show the extensibility of our vectorized kernels to processing units with a varying of vector lanes. © 2019 IEEE.

关键词： Sorting

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Fast and parallel Computation of the Discrete Periodic Radon Transform on GPUs, multi-core CPUs and FPGAs 25

Fast and Parallel Computation of the Discrete Periodic Radon...

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25th IEEE international conference on Image processing (ICIP)

作者： Carranza, Cesar Pattichis, Marios Llamocca, Daniel Pontificia Univ Catolica Peru Secc Elect & Elect Lima 32 Peru Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA Oakland Univ Dept Elect & Comp Engn Rochester MI 48063 USA

ISBN: (纸本)9781479970612

the Discrete Periodic Radon Transform (DPRT) has many important applications in reconstructing images from their projections and has recently been used in fast and scalable architectures for computing 2D convolutions. Unfortunately, the direct computation of the DPRT involves O(N-3) additions and memory accesses that can be very costly in single-core architectures. the current paper presents new and efficient algorithms for computing the DPRT and its inverse on multi-core CPUs and GPUs. the results are compared against specialized hardware implementations (FPGAs/ASICs). the results provide significant evidence of the success of the new algorithms. On an 8-core CPU (Intel Xeon), with support for two threads per core, FastDirDPRT and FastDirInvDPRT achieve a speedup of approximately 10x (up to 12:83x) over the single-core CPU implementation. On a 2048-core GPU (GTX 980), FastRayDPRT and FastRayInvDPRT achieve speedups in the range of 526 (for 127 x 127) to 873 (for 1021 x 1021), which approximate ideal speedups of what can be achieved. the DPRT can be computed exactly and in real-time (30 frames per second) for 1471x1471 images using FastRayDPRT on the GPU. Furthermore, the GPU algorithms approximate the performance of an efficient FPGA implementation using 2N parallel cores at 100MHz.

关键词： Discrete Periodic Radon Transform parallel Architecture Multi-core CPU GPU FPGA

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Optimizing Machine Learning algorithms on Multi-core and Many-core architectures using thread and Data Mapping 26

Optimizing Machine Learning Algorithms on Multi-core and Man...

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Serpa, Matheus S. Krause, Arthur M. Cruz, Eduardo H. M. Navaux, Philippe O. A. Pasin, Marcelo Felber, Pascal Fed Univ Rio Grande Sul UFRGS Inst Informat Porto Alegre RS Brazil Univ Neuchatel Neuchatel Switzerland

ISBN: (纸本)9781538649756

Driven by the development of new technologies such as personal assistants or autonomous cars, machine learning has rapidly become one of the most active fields in computer science. the algorithms at the core of machine learning are notoriously demanding in terms of resources. It is therefore of paramount importance to optimize their operation on modern processors. Several approaches have been proposed to accelerate machine learning on GPUs and massively parallel computers, as well as dedicated ASICs. In this paper, we focus on Intel's multi-core Xeon and many-core accelerator Xeon Phi Knights Landing, which can host several hundreds of threads on the same CPU. In such architectures, thread and data mapping are keys for performance. We study the impact of mapping strategies, revealing that, with smart mapping policies, one can indeed significantly speed up machine learning applications on manycore architectures. Execution time was reduced by up to 25.2% and 18.5% on Intel Xeon and Xeon Phi KNL, respectively.

关键词： Machine learning thread mapping Data mapping Memory accesses

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PRINS: processing-in-Storage Acceleration of Machine Learning

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2018年第5期17卷 889-896页

作者： Kaplan, Roman Yavits, Leonid Ginosar, Ran Technion Israel Inst Technol Dept Elect Engn IL-3547902 Haifa Israel

Machine learning algorithms have become a major tool in various applications. the high-performance requirements on large-scale datasets pose a challenge for traditional von Neumann architectures. We present two machine learning implementations and evaluations on PRINS, a novel processing-in-storage system based on resistive content addressable memory (ReCAM). PRINS functions simultaneously as a storage and a massively parallel associative processor. PRINS processing-in-storage resolves the bandwidth wall faced by near-data von Neumann architectures, such as three-dimensional DRAM and CPU stack or SSD with embedded CPU, by keeping the computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that PRINS-based processing-in-storage architecture may outperform existing in-storage designs and acceleratorbased designs. Multiple performance comparisons for the ReCAM processing-in-storage implementations ofK-means and K-nearest neighbors are performed. Compared platforms include CPU, GPU, FPGA, and Automata Processor. We show that PRINSmay achieve an order-of-magnitude speedup and improved power efficiency relative to all compared platforms.

关键词： Near-data processing associative processing processing-in-storage processing-in-memory RRAM CAM memristors

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Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores 26

Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Trabes, Guillermo Gil-Costa, Veronica Printista, Marcela Marin, Mauricio Univ Nacl San Luis Dept Informat LIDIC San Luis Argentina Univ Nacl San Luis San Luis Argentina CCT San Luis CONICET San Luis Argentina Univ Santiago Chile CeBiB Santiago Chile

ISBN: (纸本)9781538649756

Computer models have been used as a bridge between parallel algorithms and hardware architectures. the Bulk-Synchronous parallel (BSP) is a well-known computing model originally devised for distributed algorithms running on clusters of single-core processors. the Multi-BSP model, that extends the classic BSP model, was recently proposed for multi-core processors. However, this model - implemented through the MulticoreBSP-for-C library-presents some restrictions such as the explicit synchronizations between the cores, introducing some challenges on which the hardware characteristics should be taken into account to properly model the parallel algorithms. therefore, we explore the suitability of these models for the Dell multi-core architecture. the objectives of this contribution are twofold. First, we model two different multi-core Dell architectures. Second, we show that a simple model with few parameters can be easily adapted to each Dell platform rather than complex models which tends to use tricky hardware parameters.

关键词： parallel computing models bulk-synchronous parallel - BSP Multi-BSP Dell multi-cores

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A Malleable Vectorized Auction Algorithm for Modern Multicore architectures 20

A Malleable Vectorized Auction Algorithm for Modern Multicor...

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20th IEEE international conference on High Performance Computing and Communications (HPCC) / 16th IEEE international conference on Smart City (SmartCity) / 4th IEEE international conference on Data Science and Systems (DSS)

作者： Sena, A. C. Marzulo, L. A. J. Nascimento, A. P. Vasconcelos, C. N. Univ Estado Rio De Janeiro Inst Matemat & Estat Rio De Janeiro Brazil Univ Fed Fluminense Inst Comp Niteroi RJ Brazil

ISBN: (纸本)9781538666142

the auction algorithm has been widely used to solve the bipartite graph matching problem and its parallel implementation is employed to find solutions in a reasonable computational time. Moreover, the new multicore architectures, besides its various cores, have a SIMD instruction set that can increase application performance when exactly the same operations are to be performed on multiple data objects. the aim of this paper is to efficiently execute the auction algorithm on these architectures. To achieve that, a vectorized version was implemented and evaluated. these versions were then run in parallel using the OpenMP library. Finally, to optimize the number of threads used during the execution, a malleable strategy is proposed and evaluated. Results show that the vectorized version outperforms the sequential one by a factor of 10, while the malleable vectorized version was able to adapt its execution to exploit the full potential of multicore architectures.

关键词： Multicore processing Heuristic algorithms Program processors Indexes Bipartite graph conferences

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