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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Serpa, Matheus S. Krause, Arthur M. Cruz, Eduardo H. M. Navaux, Philippe O. A. Pasin, Marcelo Felber, Pascal Fed Univ Rio Grande Sul UFRGS Inst Informat Porto Alegre RS Brazil Univ Neuchatel Neuchatel Switzerland

ISBN: (纸本)9781538649756

Driven by the development of new technologies such as personal assistants or autonomous cars, machine learning has rapidly become one of the most active fields in computer science. the algorithms at the core of machine learning are notoriously demanding in terms of resources. It is therefore of paramount importance to optimize their operation on modern processors. Several approaches have been proposed to accelerate machine learning on GPUs and massively parallel computers, as well as dedicated ASICs. In this paper, we focus on Intel's multi-core Xeon and many-core accelerator Xeon Phi Knights Landing, which can host several hundreds of threads on the same CPU. In such architectures, thread and data mapping are keys for performance. We study the impact of mapping strategies, revealing that, with smart mapping policies, one can indeed significantly speed up machine learning applications on manycore architectures. Execution time was reduced by up to 25.2% and 18.5% on Intel Xeon and Xeon Phi KNL, respectively.

关键词： Machine learning thread mapping Data mapping Memory accesses

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PRINS: processing-in-Storage Acceleration of Machine Learning

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2018年第5期17卷 889-896页

作者： Kaplan, Roman Yavits, Leonid Ginosar, Ran Technion Israel Inst Technol Dept Elect Engn IL-3547902 Haifa Israel

Machine learning algorithms have become a major tool in various applications. the high-performance requirements on large-scale datasets pose a challenge for traditional von Neumann architectures. We present two machine learning implementations and evaluations on PRINS, a novel processing-in-storage system based on resistive content addressable memory (ReCAM). PRINS functions simultaneously as a storage and a massively parallel associative processor. PRINS processing-in-storage resolves the bandwidth wall faced by near-data von Neumann architectures, such as three-dimensional DRAM and CPU stack or SSD with embedded CPU, by keeping the computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that PRINS-based processing-in-storage architecture may outperform existing in-storage designs and acceleratorbased designs. Multiple performance comparisons for the ReCAM processing-in-storage implementations ofK-means and K-nearest neighbors are performed. Compared platforms include CPU, GPU, FPGA, and Automata Processor. We show that PRINSmay achieve an order-of-magnitude speedup and improved power efficiency relative to all compared platforms.

关键词： Near-data processing associative processing processing-in-storage processing-in-memory RRAM CAM memristors

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Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores 26

Multi-BSP vs. BSP: A Case of Study for Dell AMD Multicores

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Trabes, Guillermo Gil-Costa, Veronica Printista, Marcela Marin, Mauricio Univ Nacl San Luis Dept Informat LIDIC San Luis Argentina Univ Nacl San Luis San Luis Argentina CCT San Luis CONICET San Luis Argentina Univ Santiago Chile CeBiB Santiago Chile

ISBN: (纸本)9781538649756

Computer models have been used as a bridge between parallel algorithms and hardware architectures. the Bulk-Synchronous parallel (BSP) is a well-known computing model originally devised for distributed algorithms running on clusters of single-core processors. the Multi-BSP model, that extends the classic BSP model, was recently proposed for multi-core processors. However, this model - implemented through the MulticoreBSP-for-C library-presents some restrictions such as the explicit synchronizations between the cores, introducing some challenges on which the hardware characteristics should be taken into account to properly model the parallel algorithms. therefore, we explore the suitability of these models for the Dell multi-core architecture. the objectives of this contribution are twofold. First, we model two different multi-core Dell architectures. Second, we show that a simple model with few parameters can be easily adapted to each Dell platform rather than complex models which tends to use tricky hardware parameters.

关键词： parallel computing models bulk-synchronous parallel - BSP Multi-BSP Dell multi-cores

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A Malleable Vectorized Auction Algorithm for Modern Multicore architectures 20

A Malleable Vectorized Auction Algorithm for Modern Multicor...

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20th IEEE international conference on High Performance Computing and Communications (HPCC) / 16th IEEE international conference on Smart City (SmartCity) / 4th IEEE international conference on Data Science and Systems (DSS)

作者： Sena, A. C. Marzulo, L. A. J. Nascimento, A. P. Vasconcelos, C. N. Univ Estado Rio De Janeiro Inst Matemat & Estat Rio De Janeiro Brazil Univ Fed Fluminense Inst Comp Niteroi RJ Brazil

ISBN: (纸本)9781538666142

the auction algorithm has been widely used to solve the bipartite graph matching problem and its parallel implementation is employed to find solutions in a reasonable computational time. Moreover, the new multicore architectures, besides its various cores, have a SIMD instruction set that can increase application performance when exactly the same operations are to be performed on multiple data objects. the aim of this paper is to efficiently execute the auction algorithm on these architectures. To achieve that, a vectorized version was implemented and evaluated. these versions were then run in parallel using the OpenMP library. Finally, to optimize the number of threads used during the execution, a malleable strategy is proposed and evaluated. Results show that the vectorized version outperforms the sequential one by a factor of 10, while the malleable vectorized version was able to adapt its execution to exploit the full potential of multicore architectures.

关键词： Multicore processing Heuristic algorithms Program processors Indexes Bipartite graph conferences

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parallel Computing for processing Data from Intelligent Transportation Systems 10th

Parallel Computing for Processing Data from Intelligent Tran...

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10th international conference on Supercomputing, ISUM 2019

作者： Denis, Jonathan Massobrio, Renzo Nesmachnow, Sergio Cristóbal, Alfredo Tchernykh, Andrei Meneses, Esteban Universidad de la República Montevideo Uruguay Universidad Veracruzana Heroica Veracruz Mexico Centro de Investigación Científica y Educación Superior de Ensenada Ensenada Mexico Centro Nacional de Alta Tecnología San José Costa Rica Instituto Tecnológico de Costa Rica Cartago Costa Rica

ISBN: (纸本)9783030380427

this article describes the application of parallel computing techniques for efficiently processing large volumes of data from ITS. this is a relevant problem in nowadays societies, especially when working under the novel paradigm of smart cities. the proposed approach applies parallel multithreading computing for processing Global Positioning System records for a case study on the Intelligent Transportation System in Montevideo, Uruguay. the experimental analysis is performed on a high performance computing platform, considering a large volume of data and different computing resources. the main results indicate that the proposed approach allows achieving good speedup values, thus reducing the execution time to process more than 120 GB of data from 921 to 77 min, when using 32 threads. In addition, a web application to illustrate the results of the proposed approach for computing the average speed of public transportation in Montevideo, Uruguay, is described. © Springer Nature Switzerland AG 2019.

关键词： parallel processing systems

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An Empirical Comparison of k-Shortest Simple Path algorithms on Multicores 18

An Empirical Comparison of <i>k</i>-Shortest Simple Path Alg...

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47th international conference on parallel processing (ICPP)

作者： Ajwani, Deepak Duriakova, Erika Hurley, Neil Meyer, Ulrich Schickedanz, Alexander Nokia Bell Labs Dublin Ireland Univ Coll Dublin Sch Comp Sci Insight Ctr Data Analyt Dublin Ireland Goethe Univ Frankfurt Germany

ISBN: (纸本)9781450365109

We consider the loop less k-shortest path (KSP) problem. Although this problem has been studied in the sequential setting for at least the last two decades, no good parallel implementations are known. In this paper, we provide (i) a first systematic empirical comparison of various KSP algorithms and heuristic optimisations, (ii) carefully engineer various parallel implementations of these sequential algorithms and (iii) perform an extensive study of these parallel implementations on a range of graph classes and multicore architectures to determine the best algorithm and parallelization strategy for different graph classes. We find that even though the worst-case complexity of the best undirected KSP algorithm O (k (m + n log n)) is significantly better than that of the popular and considerably simpler directed KSP algorithm O(kn(m + n log n)), the two algorithms are fairly competitive in terms of their empirical performance on small diameter graphs. Furthermore, we show that a few simple optimisations help to bridge the gap between these KSP algorithms even more. However, on moderate to large diameter graphs, the undirected KSP algorithm is considerably faster than the directed algorithms, both in sequential and parallel settings. In terms of the parallelisation strategy, simply replacing the shortest path subroutine by parallel A-stepping algorithm can provide a good speed-up for many KSP algorithms on random graphs. In contrast, for graphs with skewed degree distribution, a more complex strategy of parallelizing the different deviations and then parallelizing the shortest path computation inside the deviations with the remaining threads, provides a better performance.

关键词： Algorithm Engineering parallel k-Shortest Path parallel Graph algorithms parallel Single Source Shortest Path

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An Axiomatization for BSP algorithms 1

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Marquer, Yoann Gava, Frederic Univ Paris East Lab Algorithms Complex & Log LACL Creteil France

ISBN: (数字)9783030050573

ISBN: (纸本)9783030050573;9783030050566

the Gurevich's thesis stipulates that sequential abstract state machines (ASMS) capture the essence of sequential algorithms. On another hand, the bulk-synchronous parallel (BSP) bridging model is a well known model for HPC algorithm design. It provides a conceptual bridge between the physical implementation of the machine and the abstraction available to a programmer of that machine. the assumptions of the BSP model are thus provide portable and scalable performance predictions on most HPC systems. We follow Gurevich's thesis and extend the sequential postulates in order to intuitively and realistically capture BSP algorithms.

关键词： BSP ASM parallel algorithm HPC Postulates Cost model

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Off-Chip Congestion Management for GPU-based Non-Uniform processing-in-Memory Networks

Off-Chip Congestion Management for GPU-based Non-Uniform Pro...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Kishore Punniyamurthy Andreas Gerstlauer The University of Texas at Austin

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

Advancements in packaging and 3D-stacking technology have enabled novel non-uniform processing-in-memory (NUPIM) architectures integrating a network of hybrid modules each with varying sizes and proportions of compute and memory. In such systems, network congestion can have a significant impact on performance and energy-efficiency scaling. At the same time, NUPIM systems often have strict power and thermal constraints, where traditional routing/redundancy or buffering based approaches to reduce congestion cannot be *** this paper, we propose a low-overhead yet scalable scheme for congestion management in off-chip networks of emerging GPU-based NUPIM systems. We note that congestion in NUPIM networks exhibits a form of tree saturation in which individually congested links form congested paths, where congestion effects due to back pressure vary across paths. Additionally, memory responses can have different performance impact due to memory divergence. Our approach exploits differences in performance impact of NUPIM traffic to mitigate congestion effects. We dynamically track congested paths and divergent data to manage priorities and accelerate performance-critical traffic. We further use critical paths knowledge to dynamically manage link widths and save I/O *** show that our congestion management outperforms a configuration with double the number of virtual channels and buffers indicating its effectiveness in managing congestion under stringent constraints. It improves performance by 15% (and up to 31%) over baseline and 10% (and up to 29%) against a memory distance based approach for congestion-affected benchmarks. Our scheme reduces 78% of I/O energy on average and up to 29% of system energy across all benchmarks.

关键词： Benchmark testing Delays Market research Systems architecture Packaging Memory management

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A Post-processing Approach in Moving Objects Detection via Feature Pyramid Networks 9

A Post-Processing Approach in Moving Objects Detection via F...

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9th international conference on parallel architectures, algorithms and Programming (PAAP)

作者： Lin, Li Wang, Bin Gu, Yinjuan Shanghai Univ Shanghai Inst Adv Commun & Data Sci Shanghai Peoples R China Shanghai Univ Sch Commun & Informat Engn Shanghai Peoples R China

ISBN: (纸本)9781538694039

Recent work has shown that Convolutional Neural Networks (CNNs) have great ability to deal with classification problems in pattern recognition field. Moving objects detection, regarding as a classification process, labels every pixel as a foreground pixel or a background pixel. In this paper, we proposed an effective post-processing approach, Residual Background Networks (ResBGNets), to improve the accuracy of moving objects detection in video sequences. Instead of learning the ground truth directly, our model learns the residual pictures between the results of existing methods and the ground truth. It benefits to understand the hidden character of each algorithm and correct the misclassification. Inside ResBGNets, we build Feature Pyramid Networks (FPN) to combine spatial information of the low-resolution level with semantical features of high-level of the high-resolution level. Evaluation performed on the 2014 CDnet dataset reveals that through our approach, most of the existing background subtraction methods can get better detection results and a significant higher FM score.

关键词： Moving objects detection convolutional neural networks background subtraction residual pictures feature pyramids

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Fine Granular parallel Algorithm for HEVC Encoding Based on Multicore Platform 10th

Fine Granular Parallel Algorithm for HEVC Encoding Based on ...

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10th international conference on Image and Graphics (ICIG)

作者： Li, Yi Hu, Dong Yin, Chuanwei Qiu, Yingcan Nanjing Univ Posts & Telecommun Key Lab Broadband Wireless Commun & Sensor Networ Educ Minist Nanjing 210003 Peoples R China Nanjing Univ Posts & Telecommun Engn Res Ctr Ubiquitous Network & Hlth Serv Educ Minist Nanjing 210003 Peoples R China Nanjing Univ Posts & Telecommun Jiangsu Prov Key Lab Image Proc & Image Commun Nanjing 210003 Peoples R China

ISBN: (纸本)9783030341138;9783030341121

Compared with the previous standards, the coding efficiency and complexity of High Efficiency Video Coding (HEVC) have been greatly improved. parallel encoding scheme based on CTU rows like wavefront parallel processing (WPP) and inter-frame wavefront (IFW) can efficiently reduce the encoding time of HEVC. However, due to the coding complexity of CTU within various rows may be quite different, WPP and IFW have the problem of unbalanced load among threads for parallel encoding tasks. To address this issue, in this paper, factors affecting coding efficiency are found by analyzing the data dependence and load relationship of intra- and inter-frame CTUs, and we propose a fine granular parallel strategy accordingly. In the meanwhile, refine the parallel granularity while maintaining the accuracy of symbol prediction requires additional context information in CABAC encoding, which leads to higher bit rate, and will reduce the efficiency of CABAC encoding. In order to decrease the bit rate without affecting the quality, we also making some modifications for the CABAC encoding. the proposed method is implemented on the Tilera-GX36 multicore platform. Experiment results show that our algorithm achieves up to 1.6 and 2.8 times speedup improvement compared with IFW and WPP respectively.

关键词： HEVC encoding CTU IFW WPP CABAC Multicore platform

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