检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,698 篇 会议
58 册 图书
55 篇 期刊文献

馆藏范围

2,811 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,851 篇 工学
- 1,634 篇 计算机科学与技术...
- 848 篇 软件工程
- 341 篇 电气工程
- 223 篇 电子科学与技术（可...
- 214 篇 信息与通信工程
- 87 篇 控制科学与工程
- 63 篇 光学工程
- 58 篇 机械工程
- 42 篇 仪器科学与技术
- 39 篇 生物医学工程（可授...
- 38 篇 生物工程
- 31 篇 材料科学与工程（可...
- 25 篇 动力工程及工程热...
- 21 篇 化学工程与技术
- 20 篇 建筑学
- 15 篇 土木工程
- 13 篇 力学（可授工学、理...
- 12 篇 交通运输工程
502 篇 理学
- 344 篇 数学
- 113 篇 物理学
- 51 篇 系统科学
- 48 篇 生物学
- 30 篇 统计学（可授理学、...
- 27 篇 化学
176 篇 管理学
- 121 篇 管理科学与工程(可...
- 63 篇 图书情报与档案管...
- 49 篇 工商管理
41 篇 医学
- 30 篇 临床医学
- 14 篇 基础医学(可授医学...
15 篇 法学
- 15 篇 社会学
9 篇 经济学
9 篇 农学
8 篇 文学
2 篇 军事学
1 篇 教育学

主题

363 篇 parallel process...
219 篇 computer archite...
205 篇 graphics process...
147 篇 parallel archite...
135 篇 graphics process...
129 篇 hardware
116 篇 parallel algorit...
112 篇 image processing
98 篇 computational mo...
94 篇 concurrent compu...
87 篇 instruction sets
86 篇 field programmab...
83 篇 algorithm design...
79 篇 multicore proces...
77 篇 signal processin...
76 篇 parallel process...
66 篇 parallel program...
60 篇 throughput
60 篇 gpu
59 篇 kernel

机构

11 篇 natl univ def te...
6 篇 college of compu...
6 篇 school of comput...
6 篇 hosei univ dept ...
6 篇 natl univ def te...
5 篇 univ aizu dept c...
5 篇 carleton univ sc...
5 篇 school of comput...
5 篇 computer science...
5 篇 inria rennes
5 篇 city university ...
4 篇 chinese acad sci...
4 篇 univ michigan ad...
4 篇 institute of com...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 univ jaume 1 dep...
4 篇 hainan internati...
4 篇 tech univ cluj n...
4 篇 department of co...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
9 篇 konrad karczewsk...
9 篇 quintana-orti en...
7 篇 dongarra jack
7 篇 kothapalli kisho...
6 篇 hannig frank
6 篇 liu jie
6 篇 su jinshu
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wyrzykowski roma...
6 篇 thulasiraman par...
5 篇 ito yasuaki
5 篇 jerzy waśniewski
5 篇 wang guojun
5 篇 geyong min
5 篇 wanlei zhou

语言

2,758 篇 英文
28 篇 其他
18 篇 中文
11 篇 俄文
2 篇 乌克兰文
1 篇 西班牙文

检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2811 条记录，以下是501-510 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

15th international Symposium on Applied Reconfigurable Computing, ARC 2019

15th International Symposium on Applied Reconfigurable Compu...

引用

15th international Symposium on Applied Reconfigurable Computing, ARC 2019

ISBN: (纸本)9783030172268

the proceedings contain 28 papers. the special focus in this conference is on Applied Reconfigurable Computing. the topics include: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan;secure Local Configuration of Intellectual Property Without a Trusted third Party;HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image processing;Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream;A Scalable FPGA-Based Architecture for Depth Estimation in SLAM;Evaluating LULESH Kernels on OpenCL FPGA;the TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based parallel Reconfigurable Computing Systems;Graph-Based Code Restructuring Targeting HLS for FPGAs;UltraSynth: Integration of a CGRA into a Control Engineering Environment;exploiting Reconfigurable Vector processing for Energy-Efficient Computation in 3D-Stacked Memories;Optimizing CNN-Based Hyperspectral Image Classification on FPGAs;Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic algorithms;reM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable architectures;Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators;hybrid Prototyping for Manycore Design and Validation;Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks;third Party CAD Tools for FPGA Design—A Survey of the Current Landscape;Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation;Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs;Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning;Supporting Columnar In-memory Formats on FPGA: the Hardware Design of Fletcher for Apache Arrow;A Novel Encoder for TDCs.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Accelerating FM-index Search for Genomic Data processing 18

Accelerating FM-index Search for Genomic Data Processing

引用

47th international conference on parallel processing (ICPP)

作者： Wang, Yuanrong Li, Xueqi Zang, Dawei Tan, Guangming Sun, Ninghui Univ Chinese Acad Sci CAS ICT SKL Comp Architecture Beijing Peoples R China Chinese Acad Sci SKL Comp Architecture ICT Beijing Peoples R China

ISBN: (纸本)9781450365109

the deluge of genomics data is incurring prohibitively high computational costs. As an important building block for genomic data processing algorithms, FM-index search occupies most of execution time in sequence alignment. Due to massive random streaming memory references relative to only small amount of computations, FM-index search algorithm exhibits extremely low efficiency on conventional architectures. this paper proposes Niubility, an accelerator for FM-index search in genomic sequence alignment. Based on our algorithm-architecture co-design analysis, we found that conventional architectures exploit low memory-level parallelism so that the available memory bandwidth cannot be fully utilized. Niubility accelerator customizes bit-wise operations and exploit data-level parallelism, that produces maximal concurrent memory accesses to saturate memory bandwidth. We implement an accelerator ASIC in a ST 28nm process that achieves up to 990x speedup over the state-of-the-art software.

关键词： Energy efficiency Hardware-acceleration Genome alignment

来源：评论

学校读者我要写书评

暂无评论

Implementation and Performance Comparison of Partitioning Techniques in Apache Spark

Implementation and Performance Comparison of Partitioning Te...

引用

international conference on Computing and Networking Technology (ICCNT)

作者： J Geetha N. G. Harshit M S Ramaiah Institute of Technology Bangalore Karnataka

Apache spark is one of the most demanded frameworks for High performance computing of Big Data. Data is growing day by day to such a large extent that the power of existing analytical tool is not sufficient. the degree of parallelism achieved directly impacts the performance of the framework. parallelism can be achieved only when there is a proper division among the dataset. Partitioning helps in this division of work. Appropriate number of partitions and related data in partition will ensure the proper storage and faster access of data. Spark provides the inbuilt libraries and also flexibility to mould the available methods of partitioning according to convenience. In this paper we discuss about the architecture of storage structure in spark, implementation of various partitioning techniques and performance comparison of those techniques.

关键词： Sparks parallel processing Big Data Partitioning algorithms Cluster computing Python Hash functions

来源：评论

学校读者我要写书评

暂无评论

An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

引用

27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. this is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. this hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

来源：评论

学校读者我要写书评

暂无评论

A Customized processing-in-Memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

引用

29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. the design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

来源：评论

学校读者我要写书评

暂无评论

Vectorized parallel Sparse Matrix-Vector Multiplication in PETSc Using AVX-512 18

Vectorized Parallel Sparse Matrix-Vector Multiplication in P...

引用

47th international conference on parallel processing (ICPP)

作者： Zhang, Hong Mills, Richard T. Rupp, Karl Smith, Barry F. Argonne Natl Lab Math & Comp Sci Div Lemont IL 60439 USA TU Wien Inst Microelect Vienna Austria

ISBN: (纸本)9781450365109

Emerging many-core CPU architectures with high degrees of single-instruction, multiple data (SIMD) parallelism promise to enable increasingly ambitious simulations based on partial differential equations (PDEs) via extreme-scale computing. However, such architectures present several challenges to their efficient use. Here, we explore the efficient implementation of sparse matrix-vector (SpMV) multiplications-a critical kernel for the workhorse iterative linear solvers used in most PDE-based simulations-on recent CPU architectures from Intel as well as the second-generation Knights Landing Intel Xeon Phi, which features many CPU cores, wide SIMD lanes, and on-package high-bandwidth memory. Traditional SpMV algorithms use compressed sparse row storage format, which is a hindrance to exploiting wide SIMD lanes. We study alternative matrix formats and present an efficient optimized SpMV kernel, based on a sliced ELLPACK representation, which we have implemented in the PETSc library. In addition, we demonstrate the benefit of using this representation to accelerate preconditioned iterative solvers in realistic PDE-based simulations in parallel.

关键词： parallel SpMV PETSc vectorization many-core Xeon Phi

来源：评论

学校读者我要写书评

暂无评论

Massively parallel Skyline Computation For processing-In-Memory architectures 18

Massively Parallel Skyline Computation For Processing-In-Mem...

引用

27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Zois, Vasileios Gupta, Divya Tsotras, Vassilis J. Najjar, Walid A. Roy, Jean-Francois Univ Calif Riverside Riverside CA 92521 USA UPMEM SAS Grenoble France

ISBN: (纸本)9781450359863

processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing the 'memory wall' crisis by prioritizing the integration of processors within DRAM. It promotes low data access latency, high bandwidth, massive parallelism, and low power consumption. the skyline operator is a known primitive used to identify those multi-dimensional points offering optimal trade-offs within a given dataset. For large multidimensional dataset, calculating the skyline is extensively compute and data intensive. Although, PIM systems present opportunities to mitigate this cost, their execution model relies on all processors operating in isolation with minimal data exchange. this prohibits direct application of known skyline optimizations which are inherently sequential, creating dependencies and large intermediate results that limit the maximum parallelism, throughput, and require an expensive merging phase. In this work, we address these challenges by introducing the first skyline algorithm for PIM architectures, called DSky. It is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing. Our experiments demonstrate that it outperforms the state-of-the-art algorithms for CPUs and GPUs, in most cases. DSky achieves 2x to 14x higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures. Furthermore, we showcase DSky's good scaling properties which are intertwined with PIM's ability to allocate resources with minimal added cost. In addition, we showcase an order of magnitude better energy consumption compared to CPUs and GPUs.

关键词： processing-in-memory skyline queries pareto dominance massive parallelism processing-near-memory load balancing

来源：评论

学校读者我要写书评

暂无评论

Analyzing the Adequacy of Readability Indicators to a Non-English Language 1

引用

10th international conference of the CLEF-Association (CLEF)

作者： Antunes, Helder Lopes, Carla Teixeira Univ Porto Fac Engn Porto Portugal INESC TEC Porto Portugal

ISBN: (数字)9783030285777

ISBN: (纸本)9783030285777;9783030285760

Readability is a linguistic feature that indicates how difficult it is to read a text. Traditional readability formulas were made for the English language. this study evaluates their adequacy to the Portuguese language. We applied the traditional formulas in 10 parallel corpora. We verified that the Portuguese language had higher grade scores (less readability) in the formulas that use the number of syllables per words or number of complex words per sentence. Formulas that use letters by words instead of syllables by words output similar grade scores. Considering this, we evaluated the correlation of the complex words in 65 Portuguese school books of 12 schooling years. We found out that the concept of complex word as a word with 4 or more syllables, instead of 3 or more syllables as originally used in traditional formulas applied to English texts, is more correlated with the grade of Portuguese school books. In the end, for each traditional readability formula, we adapted it to the Portuguese language performing a multiple linear regression in the same dataset of school books.

关键词： Readability Portuguese language Text simplification Natural language processing

来源：评论

学校读者我要写书评

暂无评论

Expediting parallel Graph Connectivity algorithms 25

Expediting Parallel Graph Connectivity Algorithms

引用

25th IEEE international conference on High Performance Computing, Data and Analytics (HiPC)

作者： Wadwekar, Mihir Kothapalli, Kishore Int Inst Informat Technol Hyderabad 500032 India

ISBN: (纸本)9781538683866

Finding whether a graph is k-connected, and the identification of its k-connected components is a fundamental problem in graph theory. For this reason, there have been several algorithms for this problem in both the sequential and parallel settings. Several recent sequential and parallel algorithms for k-connectivity rely on one or more breadth-first traversals of the input graph. While BFS can be made very efficient in a sequential setting, the same cannot be said in the case of parallel environments. A major factor in this difficulty is due to the inherent requirement to use a shared queue, balance work among multiple threads in every round, synchronization, and the like. Optimizing the execution of BFS on many current parallel architectures is therefore quite challenging. For this reason, it can be noticed that the time spent by the current parallel graph connectivity algorithms on BFS operations is usually a significant portion of their overall runtime. In this paper, we study how one can, in the context of algorithms for graph connectivity, mitigate the practical inefficiency of relying on BFS operations in parallel. Our technique suggests that such algorithms may not require a BFS of the input graph but actually can work with a sparse spanning subgraph of the input graph. the incorrectness introduced by not using a BFS spanning tree can then be offset by further post-processing steps on suitably defined small auxiliary graphs. Our experiments on finding the 2, and 3-connectivity of graphs on Nvidia K40c GPUs improve the state-of-the-art on the corresponding problems by a factor 2.2x, and 2.1x respectively.

关键词： Testing parallel algorithms Phase change random access memory Graphics processing units Data structures Synchronization

来源：评论

学校读者我要写书评

暂无评论

Detect Wi-Fi Network Attacks Using parallel Genetic Programming 10

Detect Wi-Fi Network Attacks Using Parallel Genetic Programm...

引用

10th international conference on Knowledge and Systems Engineering (KSE)

作者： Van Canh Vu Tuan-Hao Hoang Le Quy Don Tech Univ Fac Informat Technol Hanoi Vietnam

ISBN: (纸本)9781538661130

Wi-Fi network have been widely used nowadays. However, Intrusion Detection System (IDS) researches on Wi-Fi network were few and difficult since there was no common dataset between researchers on this area. Recently, Kolias et al. [2] published a comprehensive Wi-Fi network dataset extracting from real Wi-Fi traces, which is called the AWID dataset. Gene programming has proven effective in detecting network attacks, but the processing time is quite slow. Today, the development of GPU technology for high-speed parallel processing, the study of parallel programming solutions is essential. In this paper, we examined the parallel Genetic Programming (Karoo GP) [13] in wireless attack detection to improve detection rates and processing time. the experiments showed that the processing time of Karoo GP was significantly improved compared to standard GP.

关键词： wireless attack detection intrusion detection system genetic programming GP in parallel

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共282页 << < 47 48 49 50 51 52 53 54 55 56 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：