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the Research on parallel Optimization of SAR Imaging R-D Algorithm Based on CUDA

The Research on Parallel Optimization of SAR Imaging R-D Alg...

引用

international conference on Communication Software and Networks, ICCSN

作者： Pei Wei Jing Du Sai Sui Yancang Chen Luoyang Electronic Equipment Test Center LEETC Luoyang China

Synthetic Aperture Radar (SAR) imaging technology is widely used in the field of remote sensing observation, navigation positioning and so on, SAR imaging is large in data scale and long in operating time. Based on the Compute Unified Device Architecture (CUDA) programming model, the SAR imaging R-D algorithm is designed and implemented for parallel optimization on the CPU-GPU heterogeneous platform and tested on the GPU Tesla K20. the test shows that the efficiency of the core steps of R-D algorithm has been greatly improved.

关键词： Graphics processing units Azimuth Imaging Instruction sets Radar polarimetry Radar imaging Programming

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High-Performance Graphics in Racket with DirectX 17th

High-Performance Graphics in Racket with DirectX

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17th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Bossard, Antoine Kanagawa Univ Grad Sch Sci 2946 Tsuchiya Hiratsuka Kanagawa 2591293 Japan

ISBN: (纸本)9783319654829;9783319654812

Nowadays, modern computer systems rely heavily on parallel processing, and not only because of the multicore CPUs bundled with any machine, even mobile devices, but more and more thanks to the parallel processing capacities of graphics processing units (GPU), general-purpose computing on graphics processing units (GPGPU) being one example. In this paper, relying on the DirectX 12 framework, we propose an innovative approach to enable parallel processing for graphical rendering on both the CPU and GPU for the popular Racket functional programming language (formerly PLT Scheme), and importantly without compromising Racket's usability and programmer-friendliness. Our performance evaluations show significant improvements with respect to execution time (x3 speed-up in some cases), CPU utilisation time (reduced by as much as 80% in some scenarios) and the frame rate when using moving graphics.

关键词： GPU parallel processing Functional Programming Scheme

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Scheduler Accelerator for TDMA Data Centers

Scheduler Accelerator for TDMA Data Centers

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Euromicro international conference on parallel, Distributed and Network-Based processing

作者： Ioannis Patronas Nikolaos Gkatzios Vasileios Kitsakis Dionysios Reisis Konstantinos Christodoulopoulos Emmanouel Varvarigos Institute of Communications and Computers (ICCS) National Technical Univ. of Athens Physics Dpt Electronics Lab Zografos Greece National Technical University of Athens School of Electrical and Computer Engineering

Today's Data Centers networks depend on optical switching to overcome the scalability limitations of traditional architectures. All optical networks most often use slotted Time Division Multiple Access (TDMA) operation;their buffers are located at the optical network edges and their organization relies on effective scheduling of the TDMA frames to achieve efficient sharing of the network resources and a collision-free network operation. Scheduling decisions have to be taken in real time, a process that becomes computationally demanding as the network size increases. Accelerators provide a solution and the present paper proposes a scheduler accelerator to accommodate a data center network divided into points of delivery (pods) of racks and exploiting hybrid electro-optical top-of-rack (ToR) switches that access an all-optical inter-rack network. the scheduler accelerator is a parallel scalable architecture with application specific processing engines. Case studies of 2, 4, 8, 16 processors configuration are presented for the processing of all the transfer TDMA time slot requests for the cases of 512 and 1024 ToR network nodes. the architecture is realized on a Xilinx VC707 board to validate the results.

关键词： Data Center Scheduler parallel algorithms FPGA accelarator

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Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU 26

Graphie: Large-Scale Asynchronous Graph Traversals on Just a...

引用

26th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Han, Wei Mawhirter, Daniel Wu, Bo Buland, Matthew Colorado Sch Mines Dept Comp Sci Golden CO 80401 USA Salesforce Louisville CO USA Colorado Sch Mines Golden CO 80401 USA

ISBN: (纸本)9781509067640

Most GPU-based graph systems cannot handle large-scale graphs that do not fit in the GPU memory. the ever-increasing graph size demands a scale-up graph system, which can run on a single GPU with optimized memory access efficiency and well-controlled data transfer overhead. However, existing systems either incur redundant data transfers or fail to use shared memory. In this paper we present Graphie, a system to efficiently traverse large-scale graphs on a single GPU. Graphie stores the vertex attribute data in the GPU memory and streams edge data asynchronously to the GPU for processing. Graphie's high performance relies on two renaming algorithms. the first algorithm renames the vertices so that the source vertices can be easily loaded to the shared memory to reduce global memory accesses. the second algorithm inserts virtual vertices into the vertex set to rename real vertices, which enables the use of a small boolean array to track active partitions. the boolean array also resides in shared memory and can be updated in constant time. the renaming algorithms do not introduce any extra overhead in the GPU memory or graph storage on disk. Graphie's runtime overlaps data transfer with kernel execution and reuses transferred data in the GPU memory. the evaluation of Graphie on 7 real-world graphs with up to 1.8 billion edges demonstrates substantial speedups over X-Stream, a state-of-the-art edge-centric graph processing framework on the CPU, and GraphReduce, an out-of-memory graph processing systems on GPUs.

关键词： Graph Traversal GPUs Out-Of-Memory processing Data Transformation

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Design and performance characterization of practically realizable graph-based security aware algorithms for hierarchical and non-hierarchical cloud architectures 6th

Design and performance characterization of practically reali...

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6th international conference on Frontier Computing, FC 2017

作者： Kale, Rahul Vishwanath Veeravalli, Bharadwaj Wang, Xiaoli Department of Electrical and Computer Engineering National University of Singapore 4 Engineering Drive 3 Singapore117576 Singapore School of Computer Science and Technology Xidian University Xi’anShaanxi710071 China

ISBN: (纸本)9789811073977

Applications processing massive amount of data demand superior time-performance and data-storage capabilities. Many organizations are exploring Cloud Computing to manage such applications because of scalability and convenience of access from different geographic locations, whereas data security and privacy are few of the major concerns preventing them from fully embracing it. Data security while maintaining time-performance becomes an important consideration for designing data placement strategies. We first present the reader with a quick survey on the recent approaches and solutions in data placement oriented problems that address security concern and then characterize the performance for graph based algorithms that are practically realizable. We evaluated the performance of conventional strategies such as, Random, T-coloring and revisited these algorithms in the view of providing maximum security. We refer to our strategy as Data Security Preferential (DSP) data placement strategy and evaluated via rigorous performance evaluation tests to identify which strategy will best suit the requirements of the user on three state-of-the-art hierarchical cloud platforms viz., FatTree, threeTier and DCell and non-hierarchical cloud platforms. © 2018, Springer Nature Singapore Pte Ltd.

关键词： Graphic methods

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Rocket Trajectory Real-time Generation System

Rocket Trajectory Real-time Generation System

引用

international conference on Communications, Circuits and Systems (ICCCAS)

作者： Yan Liu Zhenhua Chen Jian Wang Weihuai Li Command and control department Wenchang Satellite Launch Center Wenchang Hainan

ISBN: (纸本)9781538693902

In this paper, a real-time rocket trajectory generation system based on super wide-angle optical camera is designed, which maps the trajectory in real time according to the flight position of the rocket. In this paper, firstly, a video acquisition system based on wide-angle lens is designed. then a rocket trajectory generation algorithm based on moving target detection is proposed. Finally, by designing CUDA parallel processing algorithm, the system has high-definition video real-time processing capability. Compared with the traditional rocket flight shooting mode, the system designed in this paper can preserve the trajectory of the rocket flight while shooting in real time. the system designed in this paper is a new display method for the rocket launching image of the space launching field.

关键词： Rockets Trajectory Real-time systems Streaming media Cameras Lenses Graphics processing units

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Efficient Mining of Recurrent Rules from a Sequence Database Using Multi-Core Processors

Efficient Mining of Recurrent Rules from a Sequence Database...

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international Symposium on Advanced Intelligent Systems

作者： SeungYong Yoon Hirohisa Seki Dept. of Computer Science and Engineering Nagoya Institute of Technology Nagoya Japan

ISBN: (纸本)9781538626344;9781538626337

Software specification mining has been studied by many researchers. Among them, Non-Redundant Recurrent Rules Miner (NR~3), proposed by Lo et al., mines recurrent rules. A recurrent rule can capture temporal patterns such as "Whenever a series of events occurs, another series of events must eventually occur", and it is particularly useful for program testing and verification to find bugs and ensure correctness of a software system. NR~3 and its successor BOB are sequential algorithms for mining non-redundant recurrent rules, and mining recurrent rules still requires considerable computational costs. In this paper, we propose a new method, called pLF-NR~3, to make NR~3 more efficient;our approach is based on LF-NR~3, an improved sequential algorithm of NR~3, and it exploits parallelism existing in NR~3. the proposed method is implemented on multi-core processors. We present some experimental results, which show the effectiveness of our proposed method.

关键词： Sequential pattern mining Recurrent rule Sequence database parallel processing Multi-core processors

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Extraction of Recursion Level parallelism for Embedded Multicore Systems 17

Extraction of Recursion Level Parallelism for Embedded Multi...

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17th Annual international conference on Embedded Computer Systems - architectures, Modeling, and Simulation (SAMOS)

作者： Aguilar, Miguel Angel Leupers, Rainer Ascheid, Gerd Eusse, Juan Fernando Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silex GmbH Herne Germany

ISBN: (纸本)9781538634370

Recursive programs that typically implement divide-and-conquer algorithms are well-suited for multicore systems, as they offer a high degree of parallelization potential. So far, existing parallelizing compilers have mainly focused on extracting other parallel patterns, such as data or pipeline level parallelism. In this paper, we propose a toolflow for the extraction of recursion level parallelism for embedded multicore systems. To achieve this, the toolflow verifies not only the mutual independence of recursive call-sites, but also selects an appropriate task granularity to ensure a good trade-off between load balancing and parallelization overhead. Profitable parallelization opportunities are implemented by using compiler directives from the OpenMP tasking model. Results show the effectiveness of our toolflow, as it is able to speedup sequential recursive programs between 2.5x and 3.8x on a quad-core platform.

关键词： Task analysis Multicore processing parallel processing Analytical models Performance analysis Static analysis Load management task analysis load management parallel processing (COMPUTERS) ANALYSIS MODELS Multi-core processors parallelism Synclitism Recursion Recursive Procedure parallelizing compilers parallelization

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An Improved Abstract GPU Model with Data Transfer 46

An Improved Abstract GPU Model with Data Transfer

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46th international conference on parallel processing Workshops (ICPPW)

作者： Carroll, thomas C. Wong, Prudence W. H. Univ Liverpool Dept Comp Sci Liverpool Merseyside England

ISBN: (纸本)9781538610442

GPUs are commonly used as coprocessors to accelerate a compute-intensive task, thanks to their massively parallel architecture. there is study into different abstract parallel models, which allow researchers to design and analyse parallel algorithms. However, most work on analysing GPU algorithms has been software based tools for profiling a GPU algorithm. Recently, some abstract GPU models have been proposed, yet they do not capture all elements of a GPU. In particular, they miss the data transfer between CPU and GPU, which in practice can cause a bottleneck and reduce performance dramatically. We propose a comprehensive model called Abstract Transferring GPU which to our knowledge is the first abstract GPU model to capture data transfer between CPU and GPU. We show via experiments, that existing abstract GPU models cannot sufficiently capture all of the actual running of a GPU algorithm time in all cases, as they do not capture data transfer. We show that by capturing data transfer with our model, we are able to obtain more accurate predictions of the GPU algorithm actual running time. It is expected that our model helps improve design and analysis of heterogeneous systems consisting of CPU and GPU, and will allow researchers to make better informed implementation decisions, as they will be aware how data transfer will affect their programs.

关键词： Graphics processors parallel architectures Data communications Modelling and prediction

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the Open Community Runtime on the Intel Knights Landing Architecture 17th

The Open Community Runtime on the Intel Knights Landing Arch...

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17th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Dokulil, Jiri Benkner, Siegfried Yaghob, Jakub Univ Vienna Fac Comp Sci Vienna Austria Charles Univ Prague Dept Software Engn Prague Czech Republic

ISBN: (纸本)9783319654829;9783319654812

the Intel Xeon Phi Knights Landing manycore processor comes with new interesting features: on-chip high-bandwidth memory and several user-selectable NUMA configurations. In this paper, we look into how these affect applications that target the Open Community Runtime (OCR), an asynchronous tasked-based runtime system for future parallel architectures. We have extended our OCR runtime to make it NUMA aware and to allow it to use the high-bandwidth memory. We have conducted a range of experiments, comparing OpenMP, TBB, our OCR implementation, and the reference OCR implementation on different machine configurations using a memory intensive seismic simulation.

关键词： Open Community Runtime Knights Landing Intel Xeon Phi High-bandwidth memory parallel runtime systems NUMA

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