Performance enhancement of a teaching-learning basedz optimizer (TLBO) for strip flatness optimization during a coiling process is proposed. the method is termed improved teaching-learning based optimization (ITLBO). ...
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ISBN:
(纸本)9783319493978;9783319493961
Performance enhancement of a teaching-learning basedz optimizer (TLBO) for strip flatness optimization during a coiling process is proposed. the method is termed improved teaching-learning based optimization (ITLBO). the new algorithm is achieved by modifying the teaching phase of the original TLBO. the design problem is set to find spool geometry and coiling tension in order to minimize flatness defects during the coiling process. Having implemented the new optimizer with flatness optimization for strip coiling, the results reveal that the proposed method gives a better optimum solution compared to the present state-of-the-art methods.
Continuous phase modulation (CPM) has been widely used in telecommunication and aeronautical telemetry system due to its high power and spectral efficiency. Non-coherent detection is a kind of feasible CPM detection m...
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ISBN:
(纸本)9781538661192
Continuous phase modulation (CPM) has been widely used in telecommunication and aeronautical telemetry system due to its high power and spectral efficiency. Non-coherent detection is a kind of feasible CPM detection method if there is large phase noise or residual carrier frequency offset. Near-optimal non-coherent sequence detection, which is based on Viterbi algorithm, has a performance close to that of maximum-likelihood sequence detection (MLSD). However, near-optimal non-coherent detection of CPM is very complicated to he implemented, and it is even more difficult to achieve a high speed due to feedback in the process of calculating branch metrics, add-compare-select (ACS), updating the beginning phase and phase reference symbol. In this paper, we first review near-optimal non-coherent detection of CPM, and then we present a high speed design of FPGA implementation for near-optimal non-coherent detection of a 64 state, 4-ary, length-3T raised cosine (3RC) CPM on Xilinx XC7VX690T device. In our scheme, the frequency pulse truncation is used to simplify the CPM detection. We propose a feedback processing in parallel for different states of CPM trellis to achieve a low latency. Furthermore, we develop a recursive implementation architecture for the process of updating the beginning phase. We achieve the CPM bit rate of 25Mbps for the on-chip processing clock of 100MHz. the results of simulation shows near-optimal non-coherent detection performs much better the coherent detection when residual carrier frequency offset or phase noise exists. It is found that the implementation can achieve a degradation in the Eb/NO from computer simulation of as small as 0.3 dB for an average BER=10(5).
In this paper, an active intelligent reflecting surface (IRS) assisted secure integrated sensing and simultaneous wireless information and power transfer system is proposed withthe power splitting (PS) model adopted....
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Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as s(C)(n) and d(C)(n) respectively. Snir proved that S-C(n...
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ISBN:
(纸本)0780387368
Parallel prefix adder is a general technique for speeding up binary addition. In unit delay model, we denote the size and depth of an n-bit prefix adder C(n) as s(C)(n) and d(C)(n) respectively. Snir proved that S-C(n) + d(C)(n) >= 2n - 2 holds for arbitrary prefix adders. Hence, a prefix adder is said to be of zero-deficiency if S-C(n) + d(C)(n) = 2n - 2. In this paper, we first propose a new architecture of zero-deficiency prefix adder dubbed Z(d), which provably has the minimal depth among all kinds of zero-deficiency prefix adders. We then design a 64-bit prefix adder Z64, which is derived from Z(d)vertical bar d=8, and compare it against several classical prefix adders of the same bit width in terms of area and delay using logical effort method. the result shows that the proposed Z(d) adder is also promising in practical VLSI design.
High voltage switchgear products always produce a great lot of parts models and design information in digital *** such products have the characteristics of series and complexity. therefor, this paper takes a certai...
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High voltage switchgear products always produce a great lot of parts models and design information in digital *** such products have the characteristics of series and complexity. therefor, this paper takes a certain series of outdoor HV isolating switchgear as an example, and multiattribute mapping parts library system has been researched and developed based on C/S mode for corporate design department, which achieves an effective classification ,dynamic management ,information integration, reuse and variant design of parts. Simultaneity, this system is seamlessly integrated withthe Inventor 2008 design software. All of these can greatly improve system efficiency and design efficiency, and shorten the product development cycle.
In this paper, a secure cooperative beamforming and artificial noise design scheme is developed for multi-pair two-way relay networks. We derive the secrecy sum rate for multi-pair two-way relaying, where each communi...
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ISBN:
(纸本)9783319218373;9783319218366
In this paper, a secure cooperative beamforming and artificial noise design scheme is developed for multi-pair two-way relay networks. We derive the secrecy sum rate for multi-pair two-way relaying, where each communication pair exchanges information through multiple friendly and cooperating relays while under the interception of multiple passive eavesdroppers. We formulate the secrecy sum rate maximization problem and show its non-convexity. We then propose a beamforming and artificial noise design scheme by transforming this problem into a series of convex problems by a tight semidefinite relaxation (SDR) and Taylor approximation. Simulations show that the proposed method converges fast with a high secure sum rate.
A vital goal of instruction is to enable learners to transfer acquired knowledge to appropriate future situations For elementary school children in middle-high-SES schools. "explicit" instruction on the Cont...
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ISBN:
(纸本)9783642134364
A vital goal of instruction is to enable learners to transfer acquired knowledge to appropriate future situations For elementary school children in middle-high-SES schools. "explicit" instruction on the Control of Variables Strategy (CVS) has proven to be very effective at promoting transfer. even after time delays. when administered by human instructors [1], [2] and when administered by our computer tutor ("TED" for Training in Experimental design) However, when the same instruction was delivered to students in low-SES schools, near-but especially far-transfer rates were lower We discuss our findings of the predictors of transfer in this population, and an initial investigation assessing the causal status of one candidate factor for far transfer. understanding the logic of CVS Finally, we discuss the potential implications of these findings for ways to adapt instruction to individual students
the paper covers architecture, circuit layout and comparative technical characteristics of the next-generation reconfigurable computer systems (RCS) based on Xilinx Virtex UltraScale FPGAs with liquid cooling. the pap...
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the paper covers architecture, circuit layout and comparative technical characteristics of the next-generation reconfigurable computer systems (RCS) based on Xilinx Virtex UltraScale FPGAs with liquid cooling. the paper contains results of design, prototyping and experimental testing of the principal technical solutions of the created computational module, and deals withthe design technology of high-performance computer systems withthe help of computational module with liquid cooling. the next-generation RCSs based on the computational module with liquid cooling provide the performance of 1 PetaFlops in a standard 47U computational cabinet withthe power of 150 kWatt, and a considerable gain in such technical and economic parameters as real and specific performance, power efficiency, mass and dimension characteristics and others in comparison with similar systems.
Our liquid simulator is mainly based on octree-staggered *** use the compact difference scheme which is often used in non-staggered grid to achieve fourth order *** modified the compact scheme suitable to adaptive oct...
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Our liquid simulator is mainly based on octree-staggered *** use the compact difference scheme which is often used in non-staggered grid to achieve fourth order *** modified the compact scheme suitable to adaptive octree-staggered *** stylized rendering procedure,we use 2D texture mapping method to generate still *** scheme smoothing in time axes is introduced to maintain temporal coherence in *** algorithm we used can reduce the stroke "twinkle" phenomenon among frames.
In the education modality known as Distance Learning (DL), the virtual learning environment (VLE) is the main platform that students use to take courses. therefore, it should be designed to meet users' expectation...
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