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检索条件"任意字段=10th International Conference on Field-Programmable Logic and Applications, FPL 2000"

共 144 条记录，以下是1-10 订阅

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10th international conference on field-programmable logic and applications, fpl 2000

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10th international conference on field-programmable logic and applications, fpl 2000

ISBN: (纸本)3540678999

the proceedings contain 101 papers. the special focus in this conference is on Network Processors and Prototyping. the topics include: the rising wave of field programmability;tightly integrated design space exploration with spatial and temporal partitioning in SPARCS;a dynamically reconfigurable FPGA-based content addressable memory for internet protocol characterization;a compiler directed approach to hiding configuration latency in chameleon processors;reconfigurable network processors based on field programmable system level integrated circuits;field programmable communication emulation and optimization for embedded system design;FPGA-based emulation;FPGA-based prototyping for product definition;implementation of virtual circuits by means of the FIPSOC devices;static and dynamic reconfigurable designs for a 2D shape-adaptive DCT;a self-reconfigurable gate array architecture;multitasking on FPGA coprocessors;design visualisation for dynamically reconfigurable systems;verification of dynamically reconfigurable logic;design of a fault tolerant FPGA;real-time face detection on a configurable hardware system;multifunctional programmable single-board CAN monitoring module;self-testing of linear segments in user-programmed FPGAs;implementing a fieldbus interface using an FPGA;area-optimized technology mapping for hybrid FPGAs;direct mapping of arbitrary components into LUT-based FPGAs;efficient embedding of partitioned circuits onto multi-FPGA boards;a placement algorithm for FPGA designs with multiple I/O standards;a mapping methodology for code trees onto LUT-based FPGAs;possibilities and limitations of applying evolvable hardware to real-world applications;a co-processor system with a virtex FPGA for evolutionary computation and system design with genetic algorithms.

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4th international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

4th International Workshop on FPGAs for Software Programmers...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, fpl 2017

ISBN: (纸本)9783800744435

the proceedings contain 10 papers. the topics discussed include: a case for better integration of host and target compilation when using OpenCL for FPGAs;PCIeHLS: an OpenCL HLS framework;SOCAO: source-to-source OpenCL compiler for Intel-Altera FPGAs;a highly efficient and comprehensive image processing library for C++-based high-level synthesis;accelerating Linux bash commands on FPGAs using partial reconfiguration;acceleration of solving quadratic assignment problems on programmable SoC using High level synthesis;spatial memory trace prediction;on the HLS design of bit-level operations and custom data types;and using GCC analysis techniques to enable parallel memory accesses in HLS.

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Internet connected fpl 10th

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10th international conference on field-programmable logic and applications, fpl 2000

作者： Fallside, Hamish Smith, Michael J. S. Xilinx Inc 2100 Logic Drive San JoseCA95124 United States University of Hawaii at Manoa 2540 Dole Street HonoluluHI96822 United States

ISBN: (纸本)3540678999

In this paper we explore the design of internet-based systems using field-programmable logic (fpl). We describe results from designing a hardware platform that connects fpl directly to an internet. this hardware platform comprises an FPGA;an Ethernet interface;storage for static and dynamic configuration;and nonvolatile configuration logic. An important feature of our hardware platform design is the implementation of network protocols that allow transfer of both application and configuration data to and from an FPGA across an internet. We provide quantitative comparisons between the implementation of network protocols in programmable logic and implementations using general-purpose processors. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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programmable system level integration brings system-on-chip design to the desktop 10th

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10th international conference on field-programmable logic and applications, fpl 2000

作者： Lafayette, Guy Lecurieux ATMEL European Marketing Manager - Programmable Logic 2 Allee Maryse Bastie Orlytech Wissous Cedex91781 France

this paper introduces a new family of standard products, called FPSLIC FPSLIC (field programmable System Level Integration Circuits), and associated design tools for programmable SoC. © Springer-Verlag Berlin Hei... 详细信息

ISBN: (纸本)3540678999

关键词： System-on-chip

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DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 60GHZ applications AND ITS FPGA IMPLEMENTATION

DESIGN OF A MULTI GBPS SINGLE CARRIER DIGITAL BASEBAND FOR 6...

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23rd international conference on field programmable logic and applications (fpl)

作者： Guntur, Surendra Jansen, Feike Hoogerbrugge, Jan Abkari, Lotfi Vos, Eric NXP Semicond Eindhoven Netherlands NXP Semicond Leuven Belgium

ISBN: (纸本)9781479900046

this paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. the baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. the demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using pi/2 QPSK modulation with a 13/16 LDPC code rate.

关键词： field programmable gate arrays parity check codes quadrature phase shift keying radiocommunication

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SYNthESIS OF thE SR PROGRAMMING LANGUAGE FOR COMPLEX FPGAS

SYNTHESIS OF THE SR PROGRAMMING LANGUAGE FOR COMPLEX FPGAS

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19th international conference on field programmable logic and applications

作者： Gasson, Nick Audsley, Neil Univ York Dept Comp Sci York YO10 5DD N Yorkshire England

ISBN: (纸本)9781424438914

Most existing approaches to targeting high-level software to FPGAs are based on extensions to C and do not map easily to the features and characteristics of modern FPGAs. these include massive parallelism and a variety of complex IP-blocks (eg. RAMs, DSPs). In this paper we discuss a hardware implementation of SR, a software language with first class concurrency and high-level IPC. We show that the language model can be implemented efficiently on an FPGA, and that it provides a natural means to encapsulate FPGA resources. We compare against a commercial C-based synthesis tool and achieve similar resource usage using a more expressive language.

关键词： field programmable gate arrays (FPGA)

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Rapid Implementation of a Partially Reconfigurable Video System with PYNQ 27

Rapid Implementation of a Partially Reconfigurable Video Sys...

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27th international conference on field programmable logic and applications (fpl)

作者： Hutchings, Brad Wirthlin, Mike Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9789090304281

Undergraduate students rapidly implement a partially-reconfigured, real-time video processor on the Xilinx PYNQ board. the video processor performs various real-time operations including Sobel edge detection, embossing, averaging, an interactive Pong game, etc., using a separate partially-reconfigurable bit-stream for each distinct function. Selection of image-processing functions is accomplished by a Python-based graphical user interface that is accessed via a Jupyter notebook. As users select image-processing functions the appropriate partial bit-stream is automatically downloaded to the FPGA. the resulting system is easily and quickly developed by several undergraduate students over a period of about 10 weeks with very little supervision. All files related to the project are available for download on Github. the productivity benefits provided by PYNQ, including Jupyter-based documentation, tutorials, and executable Python code greatly ease development effort making PYNQ an excellent FPGA platform for education.

关键词： Streaming media Hardware field programmable gate arrays Pipelines Tutorials Documentation Real-time systems

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F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network 27

F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network

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27th international conference on field programmable logic and applications (fpl)

作者： Fan, Hongxiang Niu, Xinyu Liu, Qiang Luk, Wayne Tianjin Univ Sch Microelect Tianjin Peoples R China Imperial Coll London Dept Comp Sch Engn London England

ISBN: (纸本)9789090304281

In recent years, 3-dimension convolutional neural networks (3D CNNs) have been widely used for video analysis, 3-dimension geometric data and medical image diagnosis. While conventional CNNs are computationally intensive, 3D CNNs push the computational requirements into another level, since each computation depends on multiple image frames. this paper describes a novel hardware architecture for a 3D convolutional neural network, and design strategies to resolve memory usage and bandwidth limitations. the proposed architecture F-C3D is implemented on zc706 at 172MHz, showing 231 times speed up compared with software implementation on 1 GHz ARM CPU, 7.4 times speed up on 3.07 GHz Intel CPU and nearly 10 times lower power consumption than GPU.

关键词： three-dimensional displays Convolution Two dimensional displays Kernel Computer architecture Hardware field programmable gate arrays

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Latency Insensitive Design Styles for FPGAs 28

Latency Insensitive Design Styles for FPGAs

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28th international conference on field programmable logic and applications (fpl)

作者： Abbas, Mustafa Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Long distance interconnect delays are not scaling well with process technology, thereby leading to long routes strongly impacting the critical path of large FPGA designs. this forces the designer to pipeline long connections, which necessitates time consuming logic redesign in traditional latency sensitive systems. Latency-insensitive design (LID) is an increasingly attractive alternative as the typical latency of long distance interconnect grows, since LID decouples the design of the interconnect from that of the computational modules. By doing so, LID simplifies timing closure, improves forward compatibility (migration of systems to future FPGAs) and makes automated system-level pipelining feasible. Modern FPGAs, such as Stratix 10 which includes pipelined interconnect, make it difficult to use traditional LID solutions without significant area and frequency overhead. We present two LID styles that are more suitable for FPGAs and compare them to traditional LID. Our best system gained 2x area efficiency and 18% speed efficiency over traditional LID. Additionally, our designs come at a minimal speed overhead of only 3% compared to that of a latency-sensitive design.

关键词： Registers field programmable gate arrays Pipeline processing Timing Relays Integrated circuit interconnections Clocks

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Optimising Sparse Matrix Vector Multiplication for Large Scale FEM problems on FPGA 26

Optimising Sparse Matrix Vector Multiplication for Large Sca...

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26th international conference on field-programmable logic and applications (fpl)

作者： Grigoras, Paul Burovskiy, Pavel Luk, Wayne Sherwin, Spencer Imperial Coll London Dept Comp London England Imperial Coll London Dept Aeronaut London England

ISBN: (纸本)9782839918442

Sparse Matrix Vector multiplication (SpMV) is an important kernel in many scientific applications. In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. We evaluate the proposed approach in the context of the spectral/hp Finite Element Method, using the local matrix assembly approach. this problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. the efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user. In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems.

关键词： field programmable gate arrays (FPGA)

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