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检索条件"任意字段=10th International Conference on Parallel and Distributed Computing, Applications and Technologies"

共 1765 条记录，以下是1721-1730 订阅

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A Droop Control Method Based on Adaptive Virtual Impedance for parallel Control of distributed Generators

A Droop Control Method Based on Adaptive Virtual Impedance f...

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international conference on Power Electronics Systems and applications (ICPESA)

作者： Taozi Mo Neng Li Zhang Zhang Junhua Li Zhenghong Zhang Jianfei Pan College of Mechatronics and Control Engineering Shenzhen University Shenzhen China

ISBN: (数字)9798350365801

ISBN: (纸本)9798350365818

Traditional droop control method cannot achieve effective reactive power distribution when distributed generators are paralleled. therefore, this paper proposes a droop control scheme based on adaptive virtual impedance to solve the problem of uneven distribution of reactive power. the proposed method calculates the impedance difference between the two distributed power sources based on the feedback of line current and voltage, and introduces the adaptive virtual impedance compensation scheme accordingly. the proposed scheme reduces the amount of data to be transmitted during communication, and the system design is simple. the simulation in this paper demonstrate that, the proposed method reduces the percentage error in reactive power distribution from 10.5% to 0.4% under load variations and from 21% to 0.1%, when there is a sudden change in the impedance of one of the lines.

关键词： Reactive power Simulation Load management Generators Real-time systems Power electronics Impedance

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Enhancing Web Service Composition Security with Formal Methods

Enhancing Web Service Composition Security with Formal Metho...

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international conference on Computer and Communications (ICCC)

作者： Li Bao School of Data Science and Application Inner Mongolia University of Technology Huhhot China

ISBN: (数字)9798331507077

ISBN: (纸本)9798331507084

this paper presents a novel approach to enhance Web service composition through the Web Service Interaction Model (IWSN). the IWSN aims to ensure accurate interaction between Web services, improve composition scalability, resolve behavioral compatibility issues during interaction, and facilitate broader adoption of service composition technologies. Based on the Kahn Process Network (KPN) for its foundation in parallel computing via data streams and channels, the proposed model establishes formal semantics using Calculus of Communication Systems. the model's properties are explored, and its application is illustrated through a case study that demonstrates its effectiveness in web service composition and interaction.

关键词： Web services Communication systems Computational modeling Scalability Semantics parallel processing Data models Calculus Computer security Streams

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Investigation into Massively parallel MIMD Architecture based IPU System through Application Benchmarking

Investigation into Massively Parallel MIMD Architecture base...

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international conference on Information Technology, Computer and Electrical Engineering (ICITACEE)

作者： Shashank Sharma Samrit Kumar Maity Krishan Gopal Gupta Abhishek Das Mohammad Sajeed Sanjay Wandhekar HPC Technologies C-DAC Pune India

We present a performance benchmarking analysis of Intelligent Processing Unit (IPU). IPU is a new architecture developed by Graphcore, specifically designed for handling Neural Network (NN) and Graph computing (GC) workloads. IPU-POD16 is a 5U server solution, from Graphcore, consisting of four IPU servers and one host server. Each IPU server (IPU M2000) consists of 4 MK2 GC200 IPU. Our performance evaluation is focused on two aspects. First -To measure throughput, considering IPU-POD16 as a single machine, Second-To assess the scalability, by varying the number of IPUs assigned to current workload. For compute workload we used the Tensorflow implementation of ResNet-50 and performed training and validation with the Imagenet dataset. Experiments are conducted to measure the performance of the IPU system with respect to scaling, precision, network latency by devising three separate strategies. We reported throughput numbers (images/second) for training and validation, with both real data and synthetic data. Our initial conclusion is that applications are easy to port and run in the IPU platform, due to availability and support of popular frameworks like tensorflow and pytorch. In order to fully utilize the capabilities of the IPU hardware platform, advanced engineering techniques are required. In this case, we measured the performance by benchmarking with limited application varieties. More study and experimentation are required to fully understand and realize the power of the architecture (computation, networking). It would also be interesting to see how applications from other domains (other than AI/ML/DL) take benefit of this new platform.

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Design space explorations for streaming accelerators using Streaming Architectural Simulator

Design space explorations for streaming accelerators using S...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Muhammad Shafiq Miquel Pericàs Nacho Navarro Eduard Ayguadé Centre of Excellence in Science and Applied Technologies (CESAT) Islamabad Pakistan JST CREST Tokyo Institute of Technology Tokyo Japan Computer Sciences Barcelona Supercomputing Center Barcelona Spain

In the recent years streaming accelerators like GPUs have been pop-up as an effective step towards parallel computing. the wish-list for these devices span from having a support for thousands of small cores to a nature very close to the general purpose computing. this makes the design space very vast for the future accelerators containing thousands of parallel streaming cores. this complicates to exercise a right choice of the architectural configuration for the next generation devices. However, accurate design space exploration tools developed for the massively parallel architectures can ease this task. the main objectives of this work are twofold. (i) We present a complete environment of a trace driven simulator named SArcs (Streaming Architectural Simulator) for the streaming accelerators. (ii) We use our simulation tool-chain for the design space explorations of the GPU like streaming architectures. Our design space explorations for different architectural aspects of a GPU like device a e with reference to a base line established for NVIDIA's Fermi architecture (GPU Tesla C2050). the explored aspects include the performation effects by the variations in the configurations of Streaming Multiprocessors Global Memory Bandwidth, Channles between SMs down to Memory Hierarchy and Cache Hierarchy. the explorations are performed using application kernels from Vector Reduction, 2D-Convolution. Matrix-Matrix Multiplication and 3D-Stencil. Results show that the configurations of the computational resources for the current Fermi GPU device can deliver higher performance with further improvement in the global memory bandwidth for the same device.

关键词： Graphics processing units Optical character recognition software Instruction sets Space exploration

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Evolution of data management systems: from uni-processor to large-scale distributed systems 12

Evolution of data management systems: from uni-processor to ...

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Proceedings of the 10th international conference on Advances in Mobile computing & Multimedia

作者： Abdelkader Hameurlain Paul Sabatier University Toulouse Cedex France

ISBN: (纸本)9781450313070

the purpose of this talk is to provide a comprehensive state of the art concerning the evolution of data management systems from uni-processor systems to large scale distributed systems. We focus our study on the query processing and optimization methods. For each environment, we recall their motivations and point out main characteristics of proposed methods, especially, the nature of decision-making (centralized or decentralized control for high level of scalability), adaptive level (intra-operator and/or inter-operator), impact of parallelism (partitioned and pipelined parallelism) and dynamicity (e.g. elasticity) of execution models.

关键词： query processing and optimization parallel and distributed database systems P2P systems heterogeneity data grid systems relational database systems data management autonomy data integration systems large scale dynamicity mobile agents

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Improving Energy Efficiency of Permissioned Blockchains Using FPGAs

Improving Energy Efficiency of Permissioned Blockchains Usin...

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international conference on parallel and distributed Systems (ICPADS)

作者： Nathania Santoso Haris Javaid AMD Singapore

Permissioned blockchains like Hyperledger Fabric have become quite popular for implementation of enterprise applications. Recent research has mainly focused on improving performance of permissioned blockchains without any consideration of their power/energy consumption. In this paper, we conduct a comprehensive empirical study to understand energy efficiency (throughput/energy) of validator peer in Hyperledger Fabric (a major bottleneck node). We pick a number of optimizations for validator peer from literature (allocated CPUs, software block cache and FPGA based accelerator). First, we propose a methodology to measure power/energy consumption of the two resulting compute platforms (CPU-only and CPU+FPGA). then, we use our methodology to evaluate energy efficiency of a diverse set of validator peer configurations, and present many useful insights. With careful selection of software optimizations and FPGA accelerator configuration, we improved energy efficiency of validator peer by 10$\times$ compared to vanilla validator peer (i.e., energy-aware provisioning of validator peer can deliver 10$\times$ more throughput while consuming the same amount of energy). In absolute terms, this means 23,000 tx/s with power consumption of 118W from a validator peer using software block cache running on a 4-core server with AMD/Xilinx Alveo U250 FPGA card. Index Terms--Energy-efficient blockchains, Hyperledger Fabric, FPGA accelerators

关键词： distributed ledger throughput Energy efficiency Software Fabrics Peer-to-peer computing Blockchains

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High Performance Matrix Inversion on a Multi-core Platform with Several GPUs

High Performance Matrix Inversion on a Multi-core Platform w...

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Euromicro conference on parallel, distributed and Network-Based Processing

作者： Pablo Ezzatti Enrique S. Quintana-Ortí Alfredo Remon Centro de Cálculo Universidad de la República Montevideo Uruguay Uruguay Depto. de Ingeniería y Universidad Jaume I Castellón Spain

Inversion of large-scale matrices appears in a few scientific applications like model reduction or optimal control. Matrix inversion requires an important computational effort and, therefore, the application of high performance computing techniques and architectures for matrices with dimension in the order of thousands. Following the recent uprise of graphics processors (GPUs), we present and evaluate high performance codes for matrix inversion, based on Gauss-Jordan elimination with partial pivoting, which off-load the main computational kernels to one or more GPUs while performing fine-grain operations on the general-purpose processor. the target architecture consists of a multi-core processor connected to several GPUs. parallelism is extracted from parallel implementations of BLAS and from the concurrent execution of operations in the available computational units. Numerical experiments on a system with two Intel QuadCore processors and four NVIDIA cl060 GPUs illustrate the efficiency and the scalability of the different implementations, which deliver over 1.2 x 10 12 floating point operations per second.

关键词： Graphics processing unit Multicore processing Partitioning algorithms parallel processing Electronic mail

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A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

A network switch using optical interconnection for high perf...

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the international conference on parallel Interconnects, PI

作者： S. Nishimura T. Kudoh H. Nishi K. Harasawa N. Matsudaira S. Akutsu K. Tasyo H. Amano RWCP Optical Interconnection Hitachi Laboratories Kokubunji Tokyo Japan RWC Tsukuba Research Center Tsukuba Japan Hitachi Communication Systems Inc. Yokohama Japan Synergetech Inc. Tsukuba Japan Keio University Yokohama Japan

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. this switch has a new architecture to support low latency "zero-copy" communication in multi-tasking environments. Eight pairs of 800-Mbit/s/spl times/12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). these implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet.

关键词： Optical switches Optical interconnections Communication switching Delay Crosstalk throughput parallel processing Computer architecture CMOS memory circuits Application specific integrated circuits

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Data Enhancement Strategy Using Reinforcement Learning And Xgboost With BlockChain Security

Data Enhancement Strategy Using Reinforcement Learning And X...

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Intelligent technologies (CONIT), international conference on

作者： S Selvapriya N Manvizhi S Ajay V K Kavya Rosario Gilmary Dept. of Information Technology IFET College of Engineering Villupuram Tamilnadu India

ISBN: (数字)9798350349900

ISBN: (纸本)9798350349917

the enormous volumes of data generated by Next Generation Sequencing (NGS) technology have transformed genomics and made efficient data analysis techniques necessary. To create data analytics applications, the extraction, transformation, and loading (ETL) process is necessary. In understanding data features, representation, storage, I/O operations, intermediate findings, in-memory analysis, and total processing time, the data format is crucial, as this study emphasizes. Data conformance is required for effective analysis since different machine learning and data mining algorithms require different types and forms of data. In this paper, we explore data format-centric optimization of the ETL process for NGS data analysis. We investigate how computing efficiency and analytical correctness are affected by the choice of data type. By using distributed computing and parallel processing, we evaluate the effectiveness of several data formats in NGS data analysis processes, such as FASTQ, BAM, and VCF. Our study offers suggestions for developing data analytics applications in the genomics field by clarifying the relationship between data format, ETL, and algorithmic needs. We also look at the trade-offs between resource usage and data format choice. In the end, our study contributes to more accurate and efficient genomics research by addressing the urgent need for well-informed data format options in NGS data analysis.

关键词： Sequential analysis Data analysis Loading Genomics Reinforcement learning parallel processing Data mining

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A Proactive Data-parallel Framework for Machine Learning 21

A Proactive Data-Parallel Framework for Machine Learning

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2021 IEEE/ACM 8th international conference on Big Data computing, applications and technologies (BDCAT '21)

作者： Guoyi Zhao Tian Zhou Lixin Gao University of Massachusetts Amherst USA University of Massachusetts Amherst USA

ISBN: (纸本)9781450391641

Data parallel frameworks become essential for training machine learning models. the classic Bulk Synchronous parallel (BSP) model updates the model parameters through pre-defined synchronization barriers. However, when a worker computes significantly slower than other workers, waiting for the slow worker will lead to excessive waste of computing resources. In this paper, we propose a novel proactive data-parallel (PDP) framework. PDP enables the parameter server to initiate the update of the model parameter. that is, we can perform the update at any time without pre-defined update points. PDP not only initiates the update but also determines when to update. the global decision on the frequency of updates will accelerate the training. We further propose asynchronous PDP to reduce the idle time caused by synchronizing parameter updates. We theoretically prove the convergence property of asynchronous PDP. We implement a distributed PDP framework and evaluate PDP with several popular machine learning algorithms including Multilayer Perceptron, Convolutional Neural Network, K-means, and Gaussian Mixture Model. Our evaluation shows that PDP can achieve up to 20X speedup over the BSP model and scale to large clusters.

关键词： stragglers machine learning gradient descent expectation-maximization asynchronous distributed computation

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