检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

30 篇 会议
2 篇 期刊文献

馆藏范围

32 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

21 篇 工学
- 18 篇 软件工程
- 15 篇 计算机科学与技术...
- 3 篇 电气工程
- 2 篇 生物工程
- 1 篇 电子科学与技术（可...
- 1 篇 信息与通信工程
- 1 篇 化学工程与技术
- 1 篇 核科学与技术
6 篇 理学
- 4 篇 数学
- 2 篇 生物学
- 1 篇 化学
- 1 篇 系统科学
- 1 篇 统计学（可授理学、...
1 篇 法学
- 1 篇 社会学

主题

9 篇 optimization
2 篇 performance
2 篇 tiles
2 篇 graphics process...
2 篇 kernel
2 篇 heuristic algori...
1 篇 compilation tech...
1 篇 dynamic optimiza...
1 篇 data specializat...
1 篇 compilers
1 篇 parallel process...
1 篇 registers
1 篇 database systems
1 篇 face detection
1 篇 performance debu...
1 篇 relays
1 篇 memory managemen...
1 篇 feedback-directe...
1 篇 garbage collecti...
1 篇 jit-compilation

机构

1 篇 north carolina s...
1 篇 peking univ peop...
1 篇 university of te...
1 篇 edgecortix inc
1 篇 inria cea grenob...
1 篇 univ fed minas g...
1 篇 cea grenoble
1 篇 department of el...
1 篇 louisiana state ...
1 篇 univ toronto ban...
1 篇 “gheorghe asachi...
1 篇 delft univ techn...
1 篇 univ toronto dep...
1 篇 dept. of compute...
1 篇 citadel investme...
1 篇 stmicroelectroni...
1 篇 univ grenoble al...
1 篇 google mountain ...
1 篇 university of ar...
1 篇 riken ccs kobe h...

作者

2 篇 hundt robert
2 篇 charles henri-pi...
2 篇 rastello fabrice
2 篇 guillon christop...
1 篇 pouchet louis-no...
1 篇 darte alain
1 篇 bogdan t. goraş
1 篇 gomez-ros j. m.
1 篇 iooss guillaume
1 篇 ronny brendel
1 篇 derumigny nicola...
1 篇 fabre christian
1 篇 sedano l.
1 篇 edler von koch t...
1 篇 campanoni simone
1 篇 holger brunst
1 篇 wei yu
1 篇 da silva anderso...
1 篇 radu l. vieriu
1 篇 liu jun

语言

32 篇 英文

检索条件"任意字段=10th International Symposium on Code Generation and Optimization, CGO 2012"

共 32 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Proceedings of the 10th Workshop on optimizations for DSP and Embedded Systems, ODES 2013 - In Conjunction with international symposium on code generation and optimization, cgo 2013

Proceedings of the 10th Workshop on Optimizations for DSP an...

引用

10th Workshop on optimizations for DSP and Embedded Systems, ODES 2013 - In Conjunction with international symposium on code generation and optimization, cgo 2013

ISBN: (纸本)9781450319058

the proceedings contain 5 papers. the topics discussed include: IR-level versus machine-level if-conversion for predicated architectures;code generation for an application-specific VLIW processor with clustered, addressable register files;towards a performance- and energy-efficient data filter cache;power devil: tool for power gating strategy selection*;and application task and data placement in embedded many-core NUMA architectures.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Proceedings - international symposium on code generation and optimization, cgo 2012

Proceedings - International Symposium on Code Generation and...

引用

10th international symposium on code generation and optimization, cgo 2012

ISBN: (纸本)9781605586359

the proceedings contain 26 papers. the topics discussed include: Panacea: towards holistic optimization of MapReduce applications;WCET-aware static locking of instruction caches;reconciling transactional conflicts with compiler's help;micro-specialization: dynamic code specialization of database management systems;scan detection and parallelization in 'inherently sequential' nested loop programs;HELIX: automatic parallelization of irregular programs for chip multiprocessing;automatic speculative DOALL for clusters;HQEMU: a multi-threaded and retargetable dynamic binary translator on Multicores;PinADX: an interface for customizable debugging with dynamic instrumentation;DeadSpy: a tool to pinpoint program inefficiencies;runtime asynchronous fault tolerance via speculation;and auto-generation and auto-tuning of 3D stencil codes on GPU clusters.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Proceedings - international symposium on code generation and optimization, cgo 2011

Proceedings - International Symposium on Code Generation and...

引用

9th international symposium on code generation and optimization, cgo 2011

ISBN: (纸本)9781612843551

the proceedings contain 28 papers. the topics discussed include: array building blocks: a dynamic compiler for data-parallel heterogeneous systems;essential abstractions in GCC;GPU programming models, optimizations and tuning;PIPS: an interprocedural extensible source-to-source compiler infrastructure for code/application transformations and instrumentations;program optimization through loop vectorization;reconciling compilers and timing analysis for safety-critical real-time systems - the WCET-aware C compiler WCC;inside X10: implementing a high-level language on distributed and heterogeneous platforms;MAO - an extensible micro-architectural optimizer;phase-based tuning for better utilization of performance-asymmetric multicore processors;dynamic register promotion of stack variables;link-time optimization for power efficiency in a tagless instruction cache;and the runtime abort graph and its application to software transactional memory optimization.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Auto-generation and auto-tuning of 3D stencil codes on GPU clusters 12

Auto-generation and auto-tuning of 3D stencil codes on GPU c...

引用

10th international symposium on code generation and optimization, cgo 2012

作者： Zhang, Yongpeng Mueller, Frank North Carolina State University Raleigh NC United States

ISBN: (纸本)9781605586359

this paper develops and evaluates search and optimization techniques for auto-tuning 3D stencil (nearest-neighbor) computations on GPUs. Observations indicate that parameter tuning is necessary for heterogeneous GPUs to achieve optimal performance with respect to a search space. Our proposed framework takes a most concise specification of stencil behavior from the user as a single formula, auto-generates tunable code from it, systematically searches for the best configuration and generates the code with optimal parameter configurations for different GPUs. this auto-tuning approach guarantees adaptive performance for different generations of GPUs while greatly enhancing programmer productivity. Experimental results show that the delivered floating point performance is very close to previous handcrafted work and outperforms other auto-tuned stencil codes by a large margin. Copyright © 2012 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Panacea: Towards holistic optimization of MapReduce applications 12

Panacea: Towards holistic optimization of MapReduce applicat...

引用

10th international symposium on code generation and optimization, cgo 2012

作者： Liu, Jun Ravi, Nishkam Chakradhar, Srimat Kandemir, Mahmut Dept. of Computer Sci. and Eng. Pennsylvania State University United States NEC Laboratories America Princeton NJ United States

ISBN: (纸本)9781605586359

MapReduce has emerged as one of the most popular programming models for data parallel enterprise applications. Despite advances in runtime, the opportunities for optimizing MapReduce applications remain largely unexplored. In this paper, we present a framework for performing holistic compiler optimizations on legacy MapReduce applications. We have identified and implemented two optimizations and evaluated them with a set of Hadoop applications on a cluster of Xeon servers. Our experiments show that performance gains of more than 3X can be achieved without user involvement. Copyright © 2012 ACM.

关键词： MapReduce

来源：评论

学校读者我要写书评

暂无评论

HELIX: Automatic parallelization of irregular programs for chip multiprocessing 12

HELIX: Automatic parallelization of irregular programs for c...

引用

10th international symposium on code generation and optimization, cgo 2012

作者： Campanoni, Simone Jones, Timothy Holloway, Glenn Reddi, Vijay Janapa Wei, Gu-Yeon Brooks, David Harvard University Cambridge United States University of Cambridge Cambridge United Kingdom University of Texas Austin United States

ISBN: (纸本)9781605586359

We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. We show that the inter-thread communication costs forced by loop-carried data dependences can be mitigated by code optimization, by using an effective heuristic for selecting loops to parallelize, and by using helper threads to prefetch synchronization signals. We have implemented HELIX as part of an optimizing compiler framework that automatically selects and parallelizes loops from general sequential programs. the framework uses an analytical model of loop speedups, combined with profile data, to choose loops to parallelize. On a six-core Intel® Core™ i7-980X, HELIX achieves speedups averaging 2.25×, with a maximum of 4.12× , for thirteen C benchmarks from SPEC CPU2000. Copyright © 2012 ACM.

关键词： optimization

来源：评论

学校读者我要写书评

暂无评论

Idempotent code generation: Implementation, Analysis, and Evaluation

Idempotent Code Generation: Implementation, Analysis, and Ev...

引用

11th IEEE/ACM international symposium on code generation and optimization (cgo)

作者： de Kruijf, Marc Sankaralingam, Karthikeyan Google Inc.

ISBN: (纸本)9781467355254;9781467355247

Leveraging idempotence for efficient recovery is of emerging interest in compiler design. In particular, identifying semantically idempotent code and then compiling such code to preserve the semantic idempotence property enables recovery with substantially lower overheads than competing software techniques. However, the efficacy of this technique depends on application-, architecture-, and compiler-specific factors that are not well understood. In this paper, we develop algorithms for the code generation of idempotent code regions and evaluate these algorithms considering how they are impacted by these factors. Without optimizing for these factors, we find that typical performance overheads fall in the range of roughly 10-15%. However, manipulating application idempotent region size typically improves the run-time performance of compiled code by 2-10%, differences in the architecture instruction set affect performance by up to 15%, and knowing in the compiler whether control flow side-effects can or cannot occur can impact performance by up to 10%. Overall, we find that, with small idempotent region and careful architecture- and application- specific tuning, it is possible to bring compiler performance overheads consistently down into the single-digit percentage range. the absolute best performance occurs when constructing the largest possible idempotent regions;to this end, however, better compiler support is needed. In the interest of spurring development in this area, we open-source our LLVM compiler implementation and make it available as a research tool.

关键词： Algorithms Design Performance

来源：评论

学校读者我要写书评

暂无评论

ANGHABENCH: A Suite with One Million Compilable C Benchmarks for code-Size Reduction 21

ANGHABENCH: A Suite with One Million Compilable C Benchmarks...

引用

19th IEEE/ACM international symposium on code generation and optimization (cgo)

作者： da Silva, Anderson Faustino Kind, Bruno Conde de Souza Magalhaes, Jose Wesley Rocha, Jeronimo Nunes Ferreira Guimaraes, Breno Campos Quinao Pereira, Fernando Magno Univ Estadual Maringa Dept Informat Maringa Parana Brazil Univ Fed Minas Gerais Dept Comp Sci Belo Horizonte MG Brazil

ISBN: (纸本)9781728186139

A predictive compiler uses properties of a program to decide how to optimize it. the compiler is trained on a collection of programs to derive a model which determines its actions in face of unknown codes. One of the challenges of predictive compilation is how to find good training sets. Regardless of the programming language, the availability of human-made benchmarks is limited. Moreover, current synthesizers produce code that is very different from actual programs, and mining compilable code from open repositories is difficult, due to program dependencies. In this paper, we use a combination of web crawling and type inference to overcome these problems for the C programming language. We use a type reconstructor based on Hindley-Milner's algorithm to produce ANGHABENCH, a virtually unlimited collection of real-world compilable C programs. Although ANGHABENCH programs are not executable, they can be transformed into object files by any C compliant compiler. therefore, they can be used to train compilers for code size reduction. We have used thousands of ANGHABENCH programs to train YACOS, a predictive compiler based on LLVM. the version of YACOS autotuned with ANGHABENCH generates binaries for the LLVM test suite over 10% smaller than clang -Oz. It compresses code impervious even to the state-of-the-art Function Sequence Alignment technique published in 2019, as it does not require large binaries to work well.

关键词： Benchmark Repository Synthesis Training

来源：评论

学校读者我要写书评

暂无评论

An automatic code overlaying technique for multicores with explicitly-managed memory hierarchies 12

An automatic code overlaying technique for multicores with e...

引用

10th international symposium on code generation and optimization, cgo 2012

作者： Jang, Choonki Lee, Jun Seo, Sangmin Lee, Jaejin Samsung Advanced Institute of Technology Samsung Electronics Yongin 446-712 Korea Republic of School of Computer Science and Engineering Seoul National University Seoul 151-744 Korea Republic of

ISBN: (纸本)9781605586359

the explicitly-managed memory hierarchies, where a hierarchy of distinct memories is exposed to the programmer and managed explicitly by software, are not only found in typical embedded processors but also found in a class of high performance multicore architectures. code overlay techniques have been widely used to execute a program whose code is bigger than the available code memory in the system. To generate an efficient overlaid executable with maximum storage savings as well as minimum performance overhead, the overlay structure should be designed carefully. In this paper, we propose an efficient code overlay technique that automatically generates an overlay structure for a given memory size for multicores with explicitly-managed memory hierarchies. We observe that finding an efficient overlay structure with minimum memory copying and run-time check overhead is similar to the problem that finds a code placement with minimum conict misses in the instruction cache. Our algorithm exploits the temporal-ordering information between functions during program execution. the information is ob- tained from profiling the program. Experimental results with 11 parallel applications on the Cell BE processor indicate that our approach is effective and promising. Copyright © 2012 ACM.

关键词： Software architecture

来源：评论

学校读者我要写书评

暂无评论

AN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs 2020

AN5D: Automated Stencil Framework for High-Degree Temporal B...

引用

18th ACM/IEEE international symposium on code generation and optimization (cgo)

作者： Matsumura, Kazuaki Zohouri, Hamid Reza Wahib, Mohamed Endo, Toshio Matsuoka, Satoshi Barcelona Supercomp Ctr Barcelona Spain Edgecortix Inc Tokyo Japan AIST Tokyo Japan Tokyo Inst Technol Tokyo Japan RIKEN CCS Kobe Hyogo Japan RWBC OIL Tokyo Japan

ISBN: (纸本)9781450370479

Stencil computation is one of the most widely-used compute patterns in high performance computing applications. Spatial and temporal blocking have been proposed to overcome the memory-bound nature of this type of computation by moving memory pressure from external memory to on-chip memory on GPUs. However, correctly implementing those optimizations while considering the complexity of the architecture and memory hierarchy of GPUs to achieve high performance is difficult. We propose AN5D, an automated stencil framework which is capable of automatically transforming and optimizing stencil patterns in a given C source code, and generating corresponding CUDA code. Parameter tuning in our framework is guided by our performance model. Our novel optimization strategy reduces shared memory and register pressure in comparison to existing implementations, allowing performance scaling up to a temporal blocking degree of 10. We achieve the highest performance reported so far for all evaluated stencil benchmarks on the state-of-the-art Tesla V100 GPU.

关键词： Stencil Computation GPU Automatic code generation Temporal Blocking

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共4页 << < 1 2 3 4 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：