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检索条件"任意字段=10th International Symposium on Parallel Architectures, Algorithms and Programming, PAAP 2019"

共 19 条记录，以下是11-20 订阅

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Hardware implementation of P systems using microcontrollers. An operating environment for implementing a partially parallel distributed architecture

Hardware implementation of P systems using microcontrollers....

引用

2008 10th international symposium on Symbolic and Numeric algorithms for Scientific Computing, SYNASC 2008

作者： Canaval, Sandra María Gómez Rodríguez, Abraham Gutiérrez Villaverde, Santiago Alonso Natural Computing Group Universidad Politécnica de Madrid Madrid Spain

ISBN: (纸本)9780769535234

Nowadays, important efforts in the research of the Transition P Systems have been focused on the simulation/ implementation of the massively parallel character of the model. the distributed implementation of P Systems has met with the communications bottleneck problem. In this sense, there are several research works on analysis for distributed architectures that are technology independent and avoiding communication collisions. Recent works present analysis on the suitability for implementing theses architectures using an universal membrane hardware/software component based on microcontrollers. these implementations are directly programming on hardware components and the resulting data is analyzed by means of a specific program which translates the execution bit code into intelligible data for researchers. the aim of this work is to present an operating environment to automate manual tasks performed during the loading, execution and interpretation of P System into distributed architectures based on microcontrollers as well as the interpretation from inner binary data representation inside of microcontrollers. © 2008 IEEE.

关键词： Microcontrollers

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A Load Balancing Strategy for Monte Carlo Method in PageRank Problem 8th

A Load Balancing Strategy for Monte Carlo Method in PageRank...

引用

8th international symposium on parallel architectures, algorithms, and programming (paap)

作者： Shao, Bo Lai, Siyan Yang, Bo Xu, Ying Lin, Xiaola Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou Guangdong Peoples R China Sun Yat Sen Univ Minist Educ Key Lab Machine Intelligence & Adv Comp Guangzhou Guangdong Peoples R China

ISBN: (纸本)9789811064425;9789811064418

PageRank algorithm is key component of a wide range of applications. Former study has demonstrated that PageRank problem can be effectively solved through Monte Carlo method. In this paper, we focus on efficiently parallel implementing Monte Carlo method for PageRank algorithm based on GPU. Aiming at GPU, a parallel implementation must consider instruction divergence on the single instruction multiple data (SIMD) compute units. Due to the fact that low-discrepancy sequences are determined sequences, we adopt the low-discrepancy sequences to simulate the random walks in PageRank computations in our load balancing strategy. Furthermore, we allocate each thread of a block to compute a random walk of each vertex with a same low-discrepancy sequence. As a result, no idle thread exists in the PageRank computations and warp execution efficiency is up to 99%. Moreover, our strategy loads the low-discrepancy sequences into shared memory to reduce the data fetch cost. the results of experiments show that our strategy can provide high efficiency for Monte Carlo method in PageRank problem in GPGPU environment.

关键词： Monte Carlo method PageRank GPGPU parallel computing Load balancing

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Speeding Up Convolution on Multi-cluster DSP in Deep Learning Scenarios 8th

Speeding Up Convolution on Multi-cluster DSP in Deep Learnin...

引用

8th international symposium on parallel architectures, algorithms, and programming (paap)

作者： Deng Wenqi Yang Zhenhao Lu Maohui Wang Gai Yang JiangPing Zheng Qilong Univ Sci & Technol China Sch Comp Sci & Technol Hefei Anhui Peoples R China

ISBN: (纸本)9789811064425;9789811064418

Recently, deep learning has achieved great success in artificial intelligent, whose superiority also brought new opportunity for the related research in embedded system. this paper focused on optimizing and speeding the convolution computing, the core operation within convolution neural network based on a multi-cluster digital signal processor, BWDSP. By taking advantage of the BWDSP's architecture and characteristics of convolution computation, a suitable parallel algorithm was designed. Based on features of convolution neural network model structure, an automatic optimization tool for convolution computing with specific arguments was presented as well. the experimental result showed that the parallel algorithm given in this paper is 9.5x faster than GEMM-based algorithm commonly used in GPU and 5.7x faster than the traditional vectorization optimization algorithm. Meanwhile, a comparison was made between the parallel algorithm and tiled-base algorithm widely adopted in system with cache hierarchies, showing that the parallel one could achieve a better performance density of 1.55 times than that of later one, meaning that the work in this paper can make full use of computing resources to make them more efficient.

关键词： Multi-cluster processor Embedded system Deep learning Convolution neural network parallel algorithm

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A pipelining strategy for accelerating convolutional networks on arm processors 10th

A pipelining strategy for accelerating convolutional network...

引用

10th international symposium on parallel architectures, algorithms and programming, paap 2019

作者： Zhou, Xin Li, Rongchun Zhang, Peng Liu, Yuntao Dou, Yong National Key Laboratory for Parallel and Distribution Processing National University of Defense Technology Changsha450001 China

Convolutional neural networks (CNN) is playing an important role in many fields. Many applications are able to run the inference process of CNN with pre-trained models on mobile devices in these days. Improving performance of embedded processors such as ARM-based CPUs makes it possible to meet the requirement of real-time processing. In this paper, a pipelining strategy is proposed to accelerate convolution networks on ARM processors. We implement a 3 × 3 convolution with Neon instructions which are single instruction and multiple data (SIMD) instructions supported by ARM processors. In order to reduce stalls in the pipeline, issue orders of instructions are rearranged according to the out-of-order execution and dual-issue mechanism on ARM processors. A tiling method is exploited to increase data reuse. the input feature map is divided into multiple 6 × 6 tiles, and the computations within the tile is highly optimized using our proposed pipelining strategy. the speedup of proposed method is 2.88 compared with gcc compiled codes on RK3288. the effect of our optimizing method is measured by a performance profiling tool, cycles and cache misses are decreased significantly. the multi-thread version implemented with openMP achieve speedup of 6.8 compared with single-thread gcc complied version. © Springer Nature Singapore Pte Ltd. 2020.

关键词： Pipelines

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parallel Reconstruction for High Resolution Multi-frame Solar Speckle Images 1

引用

11th international symposium on parallel architectures, algorithms and programming, paap 2020

作者： Zhu, Lingxiao Jiang, Murong Fu, Pengming Chui, Wenhao School of Information Science and Engineering Yunnan University Kunming China

ISBN: (数字)9789811600104

ISBN: (纸本)9789811600098

the high resolution reconstruction of solar speckle image is an important research issue in the field of astronomical observation. Due to the influence of atmospheric turbulence, the astronomical images obtained by ground-based optical telescope will be blurred or degraded seriously, which needs to be reconstructed by image restoration method. Most of the existing regularization methods deal with a single frame image. the more image features are, the better the reconstruction effect is. However, the poor quality of the reconstructed image is caused by the insufficient features of a single solar speckle image. In this paper, we combined the complementary relationship between multi-frame speckle images to establish a multi-frame blind restoration model suitable for solar speckle image reconstruction, used genetic algorithm to select regularization parameters and realized multi-frame block reconstruction in parallel. the experimental results show that the proposed method can restore the solar speckle image well, and the reconstruction speed is fast, which can meet the requirements of astronomical observation. © 2021, Springer Nature Singapore Pte Ltd.

关键词： Image reconstruction

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Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator

Improved parameterized efficient FPGA implementations of par...

引用

IEEE international symposium on Signal Processing and Information Technology (ISSPIT)

作者： Sami Hasan Said Boussakta Alex Yakovlev School of Electrical Electronic and Computer Engineering University of Newcastle UK

Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. this improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156 FPGA board to achieve lower power consumption of (820 mW) and a (27%-44%) less device utilization at a maximum frequency of up to (231 MHz) using Xilinx System Generator. the improved parameterized FPGA implementation is a system-level abstraction of hardware-oriented parallel programming, as an alternative to gate-level Hardware Descriptive Language (HDL), to satisfy the high performance computation of parallel multidimensional filtering algorithms at a minimal development-to-market time.

关键词： Delay Finite impulse response filter

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Hardware Implementation of P Systems Using Microcontrollers. An Operating Environment for Implementing a Partially parallel Distributed Architecture

Hardware Implementation of P Systems Using Microcontrollers....

引用

international symposium on Symbolic and Numeric algorithms for Scientific Computing (SYNASC)

作者： Sandra Maria Gomez Canaval Abraham Gutierrez Rodriguez Santiago Alonso Villaverde Natural Computing Group Universidad Politecnica de Madrid Madrid Spain

Nowadays, important efforts in the research of the Transition P Systems have been focused on the simulation/implementation of the massively parallel character ofthe model. the distributed implementation of P Systems hasmet with the communications bottleneck problem. In thissense, there are several research works on analysis for distributed architectures that are technology independent and avoiding communication collisions. Recent works presentanalysis on the suitability for implementing theses architectures using an universal membrane hardware/software component based on microcontrollers. these implementations are directly programming on hardware components and the resulting data is analyzed by means of a specific program which translates the execution bit code into intelligible data for researchers. the aim of this work is to present an operating environment to automate manual tasks performed during the loading, execution and interpretation of P System into distributed architectures based on microcontrollers as well as the interpretation from inner binary data representation inside of microcontrollers.

关键词： Hardware Microcontrollers Biomembranes Computer architecture Independent component analysis Biological system modeling Power system modeling Evolution (biology) Network topology Scientific computing

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Adaptivity in Risk and Emergency Management Applications on Pervasive Grids

Adaptivity in Risk and Emergency Management Applications on ...

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Carlo Bertolli Gabriele Mencagli Marco Vanneschi Department of Computer Science University of Pisa Pisa Italy

Pervasive grid computing platforms are composed of a variety of fixed and mobile nodes, interconnected through multiple wireless and wired network technologies. Pervasive grid Applications must adapt themselves to the state of their surrounding environment which includes environmental data (e.g. collected from sensors) and the state of the used resources (e.g. network or node states). Adaptation is especially important if we consider complex high-performance pervasive grid applications, such as intelligent transportation and emergency management. In this paper we investigate how to define adaptivity for complex pervasive grid applications by providing multiple versions of application parallel modules. the versions are defined by exploiting different sequential algorithms and parallelization techniques. We introduce performance analysis tools for versions, which allow us to define specific selection policies of the best version to be executed, depending on the context. We show how each version is best suited to be executed on two application scenarios, also by means of experiments. To synthesize the contributions of this paper we introduce the ASSISTANT programming model, for adaptive pervasive grid applications.

关键词： Disaster management Risk management Grid computing Pervasive computing Floods Mobile computing Performance analysis parallel programming Application software Intelligent sensors

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dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core

dIP: A Non-intrusive Debugging IP for Dynamic Data Race Dete...

引用

international symposium on parallel architectures, algorithms and Networks (ISPAN)

作者： Chi-Neng Wen Shu-Hsuan Chou Tien-Fu Chen National Chung Cheng University Chiayi Taiwan

Traditional debug facilities are limited in providing debugging requirements for multicore parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. this work presents a fast and feasible hardware-assistant solution for many-core non-intrusive debugging. the key idea is to keep tracks of data accesses of shared memory areas and their lock synchronization activities by proposed data structures in proposed debugging IP (dIP). A page-based shared variable cache is provided to keep shared variables as long as possible, and an inexpensive pluggable off-chip RAM can eliminate the false-positive rate efficiently. To decrease the debugging traffic block, this work provides a thread library to specify shared memory/lock events and transmit those events to the dIP by a small proper hardware co-processor (eXtend dIP) of each core. Our experimental result shows the debugging traffic block (worse-case) by increasing cores, and adding tolerance buffers in XdIP can efficiently ease off. Moreover, the real workloads (SPLASH-2, MPEG-4, and H.264) are executed by the dIP non-instructive race-detection with only 4.7%~12.2% slow down in average. Finally, the hardware cost of dIP is also low when the growing of many-core.

关键词： Random access memory Hardware Multicore processing parallel programming Computer bugs Software debugging Data structures Read-write memory Yarn Libraries

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