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检索条件"任意字段=10th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2020"

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Proceedings of ia3 2020: 10th workshop on irregular applications: architectures and algorithms, Held in conjunction with SC 2020: the International Conference for High Performance Computing, Networking, Storage and Analysis

Proceedings of IA3 2020: 10th Workshop on Irregular Applicat...

引用

10th workshop on irregular applications: architectures and algorithms, ia3 2020

ISBN: (纸本)9780738110905

the proceedings contain 8 papers. the topics discussed include: accelerating domain propagation: an efficient GPU-parallel algorithm over sparse matrices;parallelizing irregular computations for molecular docking;reducing queuing impact in irregular data streaming applications;supporting irregularity in throughput-oriented computing by SIMT-SIMD integration;DistDGL: distributed graph neural network training for billion-scale graphs;labeled triangle indexing for efficiency gains in distributed interactive subgraph search;distributed memory graph coloring algorithms for multiple GPU;and performance evaluation of the vectorizable binary search algorithms on an FPGA platform.

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ia3 2020: 10th workshop on irregular applications: architectures and algorithms

IA3 2020: 10th Workshop on Irregular Applications: Architect...

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workshop on irregular applications: Architecture and algorithms (ia3)

Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. this may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original conference proceedings.

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Performance Evaluation of the Vectorizable Binary Search algorithms on an FPGA Platform 10

Performance Evaluation of the Vectorizable Binary Search Alg...

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10th IEEE/ACM workshop on irregular applications - architectures and algorithms (ia3)

作者： Jin, Zheming Finkel, Hal Argonne Natl Lab Leadership Comp Facil 9700 S Cass Ave Argonne IL 60439 USA

ISBN: (纸本)9781665415576

Field-programmable gate arrays (FPGAs) are becoming promising heterogeneous computing components. In the meantime, high-level synthesis has been pushing the FPGA-based development from a register-transfer level to a high-level-language design flow using the OpenCL and C/C++ programming languages. the performance of binary search applications is often associated with irregular memory access patterns to off-chip memory. In this paper, we implement the binary search algorithms using OpenCL, and evaluate their performance on an Intel Arria 10 based FPGA platform. Based on the evaluation results, we optimize the grid search in XSBench by vectorizing and replicating the binary search kernel. We identify the computational overhead in the implementations of the vectorizable binary search algorithms, and overcome it by grouping work-items into work-groups. Our optimizations improve the performance of the grid search using the classic binary search by a factor of 1.75 on the FPGA.

关键词： irregular memory access binary search FPGA OpenCL

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Reducing Queuing Impact in irregular Data Streaming applications 10

Reducing Queuing Impact in Irregular Data Streaming Applicat...

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10th IEEE/ACM workshop on irregular applications - architectures and algorithms (ia3)

作者： Timcheck, Stephen W. Buhler, Jeremy D. Washington Univ Dept Comp Sci & Engn St Louis MO 63110 USA

ISBN: (纸本)9781665415576

throughput-oriented streaming applications on massive data sets are a prime candidate for parallelization on wide-SIMD platforms, especially when inputs are independent of one another. Many such applications are represented as a pipeline of compute nodes connected by directed edges. Here, we study applications with irregular data flow, i.e., those where the number of outputs produced per input to a node is data-dependent and unknown a priori. Moreover, we target these applications to architectures (GPUs) where different nodes of the pipeline execute cooperatively on a single wide-SIMD processor. To promote greater SIMD parallelism, irregular application pipelines can utilize queues to gather and compact multiple data items between nodes. However, the decision to introduce a queue between two nodes must trade off benefits to occupancy against costs associated with queue reading, writing, and management. Moreover, once queues are introduced to an application, their relative sizes impact the frequency with which the application switches between nodes, incurring scheduling and context-switching overhead. this work examines two optimization problems associated with queues. First, we consider which pairs of successive nodes in a pipeline should have queues between them to maximize overall application throughput. Second, given a fixed total budget for queue space, we consider how to choose the relative sizes of inter-node queues to minimize the frequency of switching between nodes. We formulate a dynamic programming approach to the first problem and give an empirically useful approximation to the second that allows for an analytical solution. Finally, we validate our theoretical results using real-world irregular streaming computations.

关键词： queuing SIMD irregular dataflow streaming

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Parallelizing irregular Computations for Molecular Docking 10

Parallelizing Irregular Computations for Molecular Docking

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10th IEEE/ACM workshop on irregular applications - architectures and algorithms (ia3)

作者： Solis-Vasquez, Leonardo Santos-Martins, Diogo Tillack, Andreas F. Koch, Andreas Eberhardt, Jerome Forli, Stefano Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany Scripps Res Inst Ctr Computat Struct Biol La Jolla CA USA

ISBN: (纸本)9781665415576

AUTODOCK is a molecular docking software widely used in computational drug design. Its time-consuming executions have motivated the development of AUTODOCK-GPU, an OpenCL-accelerated version that can run on GPUs and CPUs. this work discusses the development of AUTODOCK-GPU from a programming perspective, detailing how our design addresses the irregularity of AuToDocK while pushing towards higher performance. Details on required data transformations, re-structuring of complex functionality, as well as the performance impact of different configurations are also discussed. While AUTODOCK-GPU reaches speedup factors of 341x on a Titan V GPU and 51x on a 48-core Xeon Platinum 8175M CPU, experiments show that performance gains are highly dependent on the molecular complexity under analysis. Finally, we summarize our preliminary experiences when porting AUTODOCK onto FPGAs.

关键词： Variable execution performance divergent control structures OpenCL molecular docking AutoDock

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Greatly Accelerated Scaling of Streaming Problems with A Migrating thread Architecture

Greatly Accelerated Scaling of Streaming Problems with A Mig...

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11th IEEE/ACM workshop on irregular applications - architectures and algorithms (ia3)

作者： Page, Brian A. Kogge, Peter M. Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

ISBN: (纸本)9781665411264

applications where continuous streams of data are passed through large data structures are becoming of increasing importance. However, their execution on conventional architectures, especially when parallelism is desired to boost performance, is highly inefficient. the primary issue is often with the need to stream large numbers of disparate data items through the equivalent of very large hash tables distributed across many nodes. this paper builds on some prior work on the Firehose streaming benchmark where an emerging architecture using threads that can migrate through memory has shown to be much more efficient at such problems. this paper extends that work to use a second generation system to not only show that same improved efficiency (10X) for larger core counts, but even signantly higher raw performance (with FPGA-based cores running at 1/10th the clock of conventional systems). Further, this additional data yields insight into what resources represent the bottlenecks to even more performance, and make a reasonable projection that implementation of such an architecture with current technology would lead to 10X performance gain on an apples-to-apples basis with conventional systems.

关键词： Emerging architectures Migrating threads Streaming Agent Based Execution Scalability

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High-Performance GPU Implementation of PageRank with Reduced Precision based on Mantissa Segmentation 8

High-Performance GPU Implementation of PageRank with Reduced...

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8th IEEE/ACM workshop on irregular applications: architectures and algorithms (ia3)

作者： Gruetzmacher, thomas Anzt, Hartwig Scheidegger, Florian Quintana-Orti, Enrique S. Karlsruhe Inst Technol Karlsruhe Germany Swiss Fed Inst Technol IBM Res Zurich Zurich Switzerland Univ Jaume 1 Castellon de La Plana Spain

ISBN: (纸本)9781728101866

We address the acceleration of the PageRank algorithm for web information retrieval on graphics processing units (GPUs) via a modular precision framework that adapts the data format in memory to the numerical requirements as the iteration converges. In detail, we abandon the IEEE 754 single- and double-precision number representation formats, employed in the standard implementation of PageRank, to instead store the data in memory in some specialized formats. Furthermore, we avoid the data duplication by leveraging a data layout based on mantissa segmentation. Our evaluation on a V100 graphics card from NVIDia shows acceleration factors of up to 30% with respect to the standard algorithm operating in double-precision.

关键词： PageRank web information retrieval large-scale irregular graphs adaptive-precision high performance

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Overcoming Load Imbalance for irregular Sparse Matrices 7

Overcoming Load Imbalance for Irregular Sparse Matrices

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7th workshop on irregular applications - architectures and algorithms (ia3)

作者： Flegar, Goran Anzt, Hartwig Univ Jaume 1 Castellon de La Plana Spain Karlsruhe Inst Technol Karlsruhe Germany Univ Tennessee Knoxville TN USA

ISBN: (纸本)9781450351362

In this paper we propose a load-balanced GPU kernel for computing the sparse matrix vector (SpMV) product. Making heavy use of the latest GPU programming features, we also enable satisfying performance for irregular and unbalanced matrices. In a performance comparison using 400 test matrices we reveal the new kernel being superior to the most popular SpMV implementations.

关键词： Sparse Matrix Vector Product GPU irregular access pattern Load Balancing

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workshop Organization

Workshop Organization

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workshop on irregular applications: Architecture and algorithms (ia3)

Provides a listing of current committee members and society officers.

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An Efficient Data Layout Transformation Algorithm for Locality-Aware Parallel Sparse FFT 7

An Efficient Data Layout Transformation Algorithm for Locali...

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7th workshop on irregular applications - architectures and algorithms (ia3)

作者： Wang, Cheng Chandrasekaran, Sunita Chapman, Barbara Univ Houston Dept Comp Sci Houston TX 77204 USA Univ Delaware Dept Comp & Informat Sci Newark DE 19716 USA SUNY Stony Brook Dept Applies Math & Stat & Comp Sci Stony Brook NY 11794 USA

ISBN: (纸本)9781450351362

Fast Fourier Transform (FFT) is one of the most important numerical algorithms widely used in numerous scientific and engineering computations. With the emergence of big data problems, however, it is challenging to acquire, process and store a sufficient amount of data to compute the FFT in the first place. Recently developed sparse FFT (sFFT) algorithm provides a solution to this problem. sFFT computes a compressed Fourier transform by using only a small subset of the input data, thus achieving significant performance improvement. While the increase in the number of cores and memory bandwidth on modern architectures provide an opportunity to improve the performance through sophisticated parallel algorithm design, sFFT is inherently complex, and numerous challenges need to be addressed. Among all the challenges, sFFT falls into the category of irregular applications in which memory access patterns are indirect and irregular that exhibit poor data locality. In this paper, we explore data layout transformation algorithms to tackle the challenge. Our approach shows that an optimized and locality-aware parallel sFFT can perform 7x faster than the original sequential sFFT library on a multicore platform. this optimized locality-aware parallel sFFT is also approximately 10x faster than the parallel FFTW.

关键词： Numerical algorithms Fourier Transforms irregular applications

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