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检索条件"任意字段=11th Asia-Pacific Conference on Advances in Computer Systems Architecture"

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Co-Synthesis of a Configurable SoC Platform based on a Network on Chip architecture 06

<bold>Co-Synthesis of a Configurable SoC Platform based on a...

引用

11th asia and South pacific Design Automation conference

作者： Véstias, Mário P. Neto, Horácio C. INESC ID Lisbon Portugal

ISBN: (纸本)0780394518

the constant increase of gate capacity and performance of configurable hardware chips made it possible to implement systems-on-chip (SoC) able to tackle the demanding requirements of many embedded systems. In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded systems. the approach has been validated with the design of a color image compression algorithm in an FPGA.

关键词： Network-on-a-chip Hardware Processor scheduling Embedded system Field programmable gate arrays computer architecture Design methodology Productivity Network topology Bandwidth

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Issues and support for dynamic register allocation

Issues and support for dynamic register allocation

引用

11th asia-pacific conference on advances in computer systems architecture

作者： Das, Abhinav Fu, Rao Zhai, Antonia Hsu, Wei-Chung Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA

ISBN: (纸本)3540400567

Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the main program. It is difficult to achieve both correctness and transparency when software-only schemes for acquiring registers are used, as described in [1]. We propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. the hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a "safe" manner, thus preserving the transparency and improving the performance of these systems.

关键词： computer architecture

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A self-reconfigurable system-on-chip architecture for satellite on-board computer maintenance

A self-reconfigurable system-on-chip architecture for satell...

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11th asia-pacific conference on advances in computer systems architecture

作者： Wu, Xiaofeng Vladimirova, Tanya Univ Surrey Dept Elect Engn Surrey Space Ctr Guildford GU2 7XH Surrey England

ISBN: (纸本)3540400567

New trends in the space industry, e.g. the development of wireless networked constellations using miniaturized satellites, have generated a pressing need for condition-based maintenance, self-repair and upgrade capabilities on-board satellites. this can be achieved by using reconfigurable hardware technologies, such as high-density Field Programmable Gate Arrays, implementing an entire on-board computer on a single chip. In this paper we present a system-on-chip architecture for on-board partial run-time reconfiguration to enable system-level functional changes on-board satellites ensuring correct operation, longer life and higher quality of service.

关键词： Microprocessor chips

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Designing a coarse-grained reconfigurable architecture using loop self-pipelining

Designing a coarse-grained reconfigurable architecture using...

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11th asia-pacific conference on advances in computer systems architecture

作者： Xu, Jinhui Wu, Guiming Dou, Yong Dong, Yazhuo Natl Univ Def Technol Sch Comp Sci Changsha 410073 Peoples R China

ISBN: (纸本)3540400567

this paper introduces LEAP(Loop Engine on Array Processor), a novel coarse-grained reconfigurable architecture which accelerates applications through Loop Self-Pipelining (LSP) technique. the LSP can provide effective execution mode for application pipelining. By mapping and distributing the expression statements of high level programming languages onto processing elements array, the LEAP can step the loop iteration automatically. the LEAP architecture has no centralized control, no centralized multi-port registers and no centralized data memory. the LEAP has the ability to exploit loop-level, instruction-level, and task-level parallelism, and it is suitable choice for stream-based application domains, such as multimedia, DSP and graphics application.

关键词： computer architecture

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A study of the performance potential for dynamic instruction hints selection

A study of the performance potential for dynamic instruction...

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11th asia-pacific conference on advances in computer systems architecture

作者： Fu, Rao Lu, Jiwei Zhai, Antonia Hsu, Wei-Chung Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA Sun Microsyst Inc Scalable Syst Grp Santa Clara CA 95054 USA

ISBN: (纸本)3540400567

Instruction hints have become an important way to communicate compile-time information to the hardware. they can be generated by the compiler and the post-link optimizer to reduce cache misses, improve branch prediction and minimize other performance bottlenecks. this paper discusses different instruction hints available on modern processor architectures and shows the potential performance impact on many benchmark programs. Some hints can be effectively selected at compile time with profile feedback. However, since the same program executable can behave differently on various inputs and performance bottlenecks may change on different micro-architectures, significant performance opportunities can be exploited by selecting instruction hints dynamically.

关键词： computer architecture

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An interface-circuit synthesis method with configurable processor core in IP-based SoC designs 06

An interface-circuit synthesis method with configurable proc...

引用

11th asia and South pacific Design Automation conference

作者： Kohara, Shunitsu Tomono, Naoki Uchida, Jumpei Miyaoka, Yuichiro Togawa, Nozomu Yanagisawa, Masao Ohtsuki, Tatsuo Waseda Univ Dept Comp Sci Tokyo Japan

ISBN: (纸本)0780394518

In SoC designs, efficient communication between the hardware IPs and the on-chip processor becomes very important, however the interface is usually affacted by the processor core specification. thus in this paper, we focus on developing an efficient interface circuit architecture for the communications between the on-chip processor and embedded hardware IP cores. we also propose a method to synthesize it. Experimental results show that our method could obtain optimal interface circuits and works well through designing a MPEG-4 encode application.

关键词： Hardware Design methodology Circuit synthesis Protocols Synthesizers computer architecture MPEG 4 Standard Application software Software systems Process design

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PMPS(3): A performance model of parallel systems

PMPS(3): A performance model of parallel systems

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11th asia-pacific conference on advances in computer systems architecture

作者： Chen Yong-ran Qi Xing-yun Qian Yue Dou Wen-hua Natl Def Univ Coll Comp Hunan 410073 Peoples R China

ISBN: (纸本)3540400567

In this paper, an open performance model framework PMPS(n) and a realization of this framework PMPS(3), including memory, I/O and network, are presented and used to predict runtime of NPB benchmarks on P4 cluster. the experimental results demonstrates that PMPS(3) can work much better than PERC for I/O intensive applications, and can do as well as PERC for memory-intensive applications. through further analysis, it is indicated that the results of the performance model can be influenced by the data correlations, control correlations and operation overlaps and which must be considered in the models to improve the prediction precision. the experimental results also showed that PMPS(n) be of great scalability.

关键词： performance model parallel I/O convolution methods

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Functional unit chaining: A runtime adaptive architecture for reducing bypass delays

Functional unit chaining: A runtime adaptive architecture fo...

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11th asia-pacific conference on advances in computer systems architecture

作者： Koh, Lih Wen Diessel, Oliver Univ New S Wales Sch Comp Sci & Engn Sydney NSW Australia

ISBN: (纸本)3540400567

Bypass delays are expected to grow beyond 1ns as technology scales. these delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affect the performance of sequential code sequences. We propose dealing with these delays through a dynamic functional unit chaining approach. We study the performance benefits of a superscalar, out-of-order processor augmented with a two-by-two array of ALUs interconnected by a fast, partial bypass network. An online profiler guides the automatic configuration of the network to accelerate specific patterns of dependent instructions. A detailed study of benchmark simulations demonstrates these first steps towards mapping binaries to a small coarse-grained array at runtime can improve instruction throughput by over 18% and 25% when the microarchitecure includes bypass delays of one cycle and two cycles, respectively.

关键词： computer architecture

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Bandwidth optimization of the EMCI for a high performance 32-bit DSP

Bandwidth optimization of the EMCI for a high performance 32...

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11th asia-pacific conference on advances in computer systems architecture

作者： Wang, Dong Hu, Xiao Chen, Shuming Guo, Yang Natl Univ Def Technol Sch Comp Sci Microelect Inst Changsha 410073 Hunan Peoples R China

ISBN: (纸本)3540400567

Memory bandwidth and interface flexibility are often bottlenecks of embedded processors. the research about memory bandwidth optimization has become a hot topic. this paper introduces four new bandwidth optimization methods for External Memory Control Interface (EMCI) integrated in high performance digit signal processors (DSP), and aims at realization of the maximum throughput of data transmission and architecture flexibility, i.e. programmable and decoupled structure, pipelined transmission of burst mode, programmable priority for arbitration, and preferential reading based on cache-line offset. the experiment results show that the performance improvement is remarkable, but different for synchronous and asynchronous memories, and depends on the application behavior. the decoupled structure proves to be of great benefit to the architectural exploration and optimization for DSPs.

关键词： Interfaces (computer)

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architecture modeling language based on UML2.0

Architecture modeling language based on UML2.0

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11th asia-pacific Software Engineering conference (APSEC 2004)

作者： Roh, S Kim, K Jeon, T Dept. Computer Science Korea University South Korea

ISBN: (纸本)0769522459

Existing ADLs (architecture Description Languages) have an advantage of formally specifying the architecture of component-based systems. But ADLs have not come into extensive use in industries since ADL users should learn a distinct notation specific to architecture, and ADLs do not address all stakes of development process that is becoming diversified everyday. On the other hand, UML is a de facto standard general modeling language for software developments as UML provides a consistent notation and various supporting tools during the whole software development cycle. A number of researches on architecture modeling based on UML have been progressed. In particular, many research results have been introduced that specialize UML by its extension mechanism in order to explicitly represent core architecture concepts that UML does not fully support.. UML2.0 embraces much more concepts that are important to architecture modeling than UML1.x. In this paper, we examine architecture modeling elements that can be represented in UML2.0 and discuss how to extend and specialize UML2.0 in order to make it more suitable for representing architectures.

关键词： Software engineering

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