the proceedings contain 108 papers. the topics discussed include: large scale on-chip networks: an accurate multi-FPGA emulation platform;LIME: a low-latency and low complexity on-chip mesochronous link with integrate...
ISBN:
(纸本)9780769532776
the proceedings contain 108 papers. the topics discussed include: large scale on-chip networks: an accurate multi-FPGA emulation platform;LIME: a low-latency and low complexity on-chip mesochronous link with integrated flow control;synthesis of flexible fault-tolerant schedules with preemption for mixed soft and hard real-time systems;embedded multicore implementation of a H.264 decoder with power management considerations;a network-on-chip channel allocator for run-time task scheduling in multi-processor system-on-chips;analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture;concurrent error detection for a network of combinational logic blocks implemented with memory embedded in FPGAs;analysis of power management strategies for a large-scale SoC platform in 65nm technology;utilization of all levels of parallelism in a processor array with subword parallelism;code generation from statecharts: simulation of wireless sensor networks;and VLSI implementation of a cryptography-oriented reconfigurable array.
this work reports the design of an embedded system using WirelessUSB technology. the paper includes the most important characteristics of the communication protocol and the results of some tests to verify the performa...
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ISBN:
(纸本)9780769532776
this work reports the design of an embedded system using WirelessUSB technology. the paper includes the most important characteristics of the communication protocol and the results of some tests to verify the performances of the network. An analytical model of the BER as a function of the transmitter output power and distances between the devices has been derived..
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders,...
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ISBN:
(纸本)9780769532776
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed We describe the possibilities of utilizing this approach in the design of Fault Tolerant systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented
this paper introduces a prototype hardware design for camera-based power management of computer display the design keeps display active only when the computer user is actually present. Otherwise it switches the displa...
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ISBN:
(纸本)9780769532776
this paper introduces a prototype hardware design for camera-based power management of computer display the design keeps display active only when the computer user is actually present. Otherwise it switches the display off to save energy. the hardware operates in real time (30fps) and consumes only 150mW of power;35 times less than software implementation.
In this paper we assess the use of High Performance Computing in design Space Exploration of a complex highly parameterized Very Long Instruction Word based system-on-a-Chip platform. Experiments show that the convent...
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ISBN:
(纸本)9780769532776
In this paper we assess the use of High Performance Computing in design Space Exploration of a complex highly parameterized Very Long Instruction Word based system-on-a-Chip platform. Experiments show that the conventional belief of linear decrease in exploration time as the number of available processors increases is discredited starting from a relatively low number of processors mainly due to communication overhead and I/O bottleneck.
Developing code for SIMD type hardware architectures is a tedious job. this is caused by the absence of both a coherent methodological framework and a hardware independent tooling. Moreover, the inherently difficult n...
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ISBN:
(纸本)9780769532776
Developing code for SIMD type hardware architectures is a tedious job. this is caused by the absence of both a coherent methodological framework and a hardware independent tooling. Moreover, the inherently difficult nature of programming dedicated massively parallel embedded processors, complicates the matter this paper describes a single framework called IRIS, to generate code for SIMD architectures. this framework is illustrated with a concrete case "Stochastic Image Quantisation". IRIS is based on an incremental construction of executable representations, which converge to the final target implementation in a semi-automated way.
Home automation is becoming a field not so futuristic: in fact, the amount of this kind of systems in the marketplace is quickly growing up. Installation of these systems allows improving comfort and security of a hou...
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ISBN:
(纸本)9780769532776
Home automation is becoming a field not so futuristic: in fact, the amount of this kind of systems in the marketplace is quickly growing up. Installation of these systems allows improving comfort and security of a house through the integration of the concepts traditionally associated with domestic environment with new generation technologies. the purpose of this paper is to describe ELIK (Easy Living In Kitchen), which is a distributed general-purpose embedded system for domotic applications, developed mainly to bring new features in the kitchen environment.
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