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检索条件"任意字段=11th Euromicro Conference on Parallel, Distributed and Network-Based Processing"

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Efficient On-Chip Multicast Routing based on Dynamic Partition Merging 28

Efficient On-Chip Multicast Routing based on Dynamic Partiti...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Tiwari, Binayak Yang, Mei Jiang, Yingtao Wang, Xiaohang Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA South China Univ Technol Sch Software Engn Guangzhou Peoples R China

ISBN: (纸本)9781728165820

networks-on-chips (NoCs) have become the mainstream communication infrastructure for chip multiprocessors (CMPs) and many-core systems. the commonly used parallel applications and emerging machine learning-based applications involve a significant amount of collective communication patterns. In CMP applications, multicast is widely used in multithreaded programs and protocols for barrier/clock synchronization and cache coherence. Multicast routing plays an important role on the system performance of a CMP. Existing partition-based multicast routing algorithms all use static destination set partition strategy which lacks the global view of path optimization. In this paper, we propose an efficient Dynamic Partition Merging (DPM)-based multicast routing algorithm. the proposed algorithm divides the multicast destination set into partitions dynamically by comparing the routing cost of different partition merging options and selecting the merged partitions with lower cost. the simulation results of synthetic traffic and PARSEC benchmark applications confirm that the proposed algorithm outperforms the existing path-based routing algorithms. the proposed algorithm is able to improve up to 23% in average packet latency and 14% in power consumption against the existing multipath routing algorithm when tested in PARSEC benchmark workloads.

关键词： networks-on-Chip (NoCs) Multicast Routing Algorithm Dynamic Partition Merging

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Mapping Method of MATLAB/Simulink Model for Embedded Many-Core Platform 28

Mapping Method of MATLAB/Simulink Model for Embedded Many-Co...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Honda, Kentaro Kojima, Sasuga Fujimoto, Hiroshi Edahiro, Masato Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan Osaka Univ Grad Sch Engn Sci Suita Osaka Japan Technol Headquarters eSOL Co Ltd Tokyo Japan Nagoya Univ Grad Sch Informat Nagoya Aichi Japan

ISBN: (纸本)9781728165820

Multi-/many-core processors are being increasingly used to reduce power consumption and improve performance. In addition, the use of Model-based Development for embedded systems has been increasing. Relative to these trends, Model-based parallelizer (MBP) has an essential role in parallelizing applications (i e, Simulink blocks) at the model level. MBP maps Simulink blocks to cores using various types of information such as block characteristics, a C code, and the multi-/many-core hardware implementation. However, MBP does not consider many-core hardware with cluster structures. this paper proposes an algorithm that decides on core allocations by considering cluster structures. the proposed algorithm combines two other algorithms: one algorithm uses the core allocation of MBP and path analysis at the clusterlevel and considers the influence of communication contention to decide on cluster allocations, and the other algorithm uses the results of MBP and remaps cluster allocations. the proposed algorithm produces better results than its component algorithms could separately. Evaluations demonstrate that the proposed algorithm obtained the better results than the existing method in terms of execution time on random and real models.

关键词： Embedded Systems Model-based Development Multi-/Many-core

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Accelerating Deep Learning using Multiple GPUs and FPGA-based 10GbE Switch 28

Accelerating Deep Learning using Multiple GPUs and FPGA-Base...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Itsubo, Tomoya Koibuchi, Michihiro Amano, Hideharu Matsutani, Hiroki Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa 2238522 Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo 1018430 Japan

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

A back-propagation algorithm following a gradient descent approach is used for training deep neural networks. Since it iteratively performs a large number of matrix operations to compute the gradients, GPUs (Graphics processing Units) are efficient especially for the training phase. thus, a cluster of computers each of which equips multiple GPUs can significantly accelerate the training phase. Although the gradient computation is still a major bottleneck of the training, gradient aggregation and parameter optimization impose both communication and computation overheads, which should also be reduced for further shortening the training time. To address this issue, in this paper, multiple GPUs are interconnected with a PCI Express (PCIe) over 10Gbit Ethernet (10GbE) technology. Since these remote GPUs are interconnected via network switches, gradient aggregation and optimizers (e.g., SGD, Adagrad, Adam, and SMORMS3) are offloaded to an FPGA-based network switch between a host machine and remote GPUs;thus, the gradient aggregation and optimization are completed in the network. Evaluation results using four remote GPUs connected via the FPGA-based 10GbE switch that implements the four optimizers demonstrate that these optimization algorithms are accelerated by up to 3.0x and 1.25x compared to CPU and GPU implementations, respectively. Also, the gradient aggregation throughput by the FPGA-based switch achieves 98.3% of the 10GbE line rate.

关键词： Optimization Switches Training Graphics processing units Acceleration Machine learning Computational modeling

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Acceleration of Radiofrequency Ablation Process for Liver Cancer Using GPU 28

Acceleration of Radiofrequency Ablation Process for Liver Ca...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Schepke, Claudio Miletto, Marcelo Cogo Fed Univ Pampa UNIPAMPA Lab Estudos Avancados LEA Campus Alegrete BR-97546550 Alegrete Brazil Fed Univ Rio Grande Sul UFRGS Grp Proc Paralelo & Distribuido GPPD Campus Vale BR-91509900 Porto Alegre RS Brazil

ISBN: (纸本)9781728165820

Computational simulation is a technique used in several research areas. In medicine, the Radiofrequency Ablation Finite Element Method (RAFEM) application was developed to simulate the RadioFrequency Ablation (RFA) process, which is a medical procedure to treat hepatic cancer. this application presents a high computational time to perform a simulation, taking up to 20 hours for simulation while the RFA procedure itself lasts from four to six minutes. Some efforts have already been carried out to obtain better performance for the application. However, none of them considered the use of GPUs, which is an architecture that can be used to accelerate finite element method applications. this work aims to propose a parallelization approach to explore ways to obtain better performance for the application through the use of GPUs to reduce the execution time under a few minutes. We adopted an iterative development process to coordinate and to generate parallel versions of the code. through this process allied to the use of GPU-accelerated code libraries, it was possible to create different versions of the application, adding improvements to each one. the results obtained with the best version showed a reduction of the computation time by up to 18 times. therefore, this improvement makes the use of RAFEM application more feasible in health treatment by reducing the waiting time for the results.

关键词： Graphics processing unit

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Off-Chip Congestion Management for GPU-based Non-Uniform processing-in-Memory networks 28

Off-Chip Congestion Management for GPU-based Non-Uniform Pro...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Punniyamurthy, Kishore Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781728165820

Advancements in packaging and 3D-stacking technology have enabled novel non-uniform processing-in-memory (NUPIM) architectures integrating a network of hybrid modules each with varying sizes and proportions of compute and memory. In such systems, network congestion can have a significant impact on performance and energy-efficiency scaling. At the same time, NUPIM systems often have strict power and thermal constraints, where traditional routing/redundancy or buffering based approaches to reduce congestion cannot be applied. In this paper, we propose a low-overhead yet scalable scheme for congestion management in off-chip networks of emerging GPU-based NUPIM systems. We note that congestion in NUPIM networks exhibits a form of tree saturation in which individually congested links form congested paths, where congestion effects due to back pressure vary across paths. Additionally, memory responses can have different performance impact due to memory divergence. Our approach exploits differences in performance impact of NUPIM traffic to mitigate congestion effects. We dynamically track congested paths and divergent data to manage priorities and accelerate performance-critical traffic. We further use critical paths knowledge to dynamically manage link widths and save I/O energy. Results show that our congestion management outperforms a configuration with double the number of virtual channels and buffers indicating its effectiveness in managing congestion under stringent constraints. It improves performance by 15% (and up to 31%) over baseline and 10% (and up to 29%) against a memory distance based approach for congestion-affected benchmarks. Our scheme reduces 78% of I/0 energy on average and up to 29% of system energy across all benchmarks.

关键词： Energy efficiency

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FastSeq: Make Sequence Generation Faster 59

FastSeq: Make Sequence Generation Faster

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Joint conference of 59th Annual Meeting of the Association-for-Computational-Linguistics (ACL) / 11th International Joint conference on Natural Language processing (IJCNLP) / 6th Workshop on Representation Learning for NLP (RepL4NLP)

作者： Yan, Yu Hu, Fei Chen, Jiusheng Bhendawade, Nikhil Ye, Ting Gong, Yeyun Duan, Nan Cui, Desheng Chi, Bingyu Zhang, Ruifei Microsoft Redmond WA 98052 USA Microsoft Res Asia Beijing Peoples R China

ISBN: (纸本)9781954085565

Transformer-based models have made tremendous impacts in natural language generation. However the inference speed is a bottleneck due to large model size and intensive computing involved in auto-regressive decoding process. We develop FastSeq framework to accelerate sequence generation without accuracy loss. the proposed optimization techniques include an attention cache optimization, an efficient algorithm for detecting repeated n-grams, and an asynchronous generation pipeline with parallel I/O. these optimizations are general enough to be applicable to Transformer-based models (e.g., T5, GPT2, and UniLM). Our benchmark results on a set of widely used and diverse models demonstrate 4-9x inference speed gain. Additionally, FastSeq is easy to use with a simple one-line code change. the source code is available at https://***/microsoft/fastseq.

关键词： Natural language processing systems

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Efficient NAS parallel Benchmark Kernels with CUDA 28

Efficient NAS Parallel Benchmark Kernels with CUDA

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： de Araujo, Gabriell Alves Griebler, Dalvan Danelutto, Marco Fernandes, Luiz Gustavo Pontifical Catholic Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres De Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Univ Pisa UNIPI Comp Sci Dept Pisa Italy

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

NAS parallel Benchmarks (NPB) are one of the standard benchmark suites used to evaluate parallel hardware and software. there are many research efforts trying to provide different parallel versions apart from the original OpenMP and MPI. Concerning GPU accelerators, there are only the OpenCL and OpenACC available as consolidated versions. Our goal is to provide an efficient parallel implementation of the five NPB kernels with CUDA. Our contribution covers different aspects. First, best parallel programming practices were followed to implement NPB kernels using CUDA. Second, the support of larger workloads (class B and C) allow to stress and investigate the memory of robust GPUs. third, we show that it is possible to make NPB efficient and suitable for GPUs although the benchmarks were designed for CPUs in the past. We succeed in achieving double performance with respect to the state-of-theart in some cases as well as implementing efficient memory usage. Fourth, we discuss new experiments comparing performance and memory usage against OpenACC and OpenCL state-of-the-art versions using a relative new GPU architecture. the experimental results also revealed that our version is the best one for all the NPB kernels compared to OpenACC and OpenCL. the greatest differences were observed for the FT and EP kernels.

关键词： Graphics processing units Kernel Benchmark testing Programming Computer architecture Hardware Standards

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Evaluating the performance and improving the usability of parallel and distributed Word Embeddings tools 28

Evaluating the performance and improving the usability of pa...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： da Silva, Matheus L. Meyer, Vinicius Kirchoff, Dionatra F. Nero, Joaquim F. S. Vieira, Renata De Rose, Cesar A. F. Pontific Catholic Univ Rio Grande PUCKS Polytech Sch Ipiranga Ave 6681 BR-90619900 Porto Alegre RS Brazil

ISBN: (纸本)9781728165820

the representation of words by means of vectors, also called Word Embeddings (WE), has been receiving great attention from the Natural Language processing (NLP) field. WE models are able to express syntactic and semantic similarities, as well as relationships and contexts of words within a given corpus. Although the most popular implementations of WE algorithms present low scalability, there are new approaches that apply High-Performance Computing (HPC) techniques. this is an opportunity for an analysis of the main differences among the existing implementations, based on performance and scalability metrics. In this paper, we present a study which addresses resource utilization and performance aspects of known WE algorithms foetid in the literature. To improve scalability and usability we propose a wrapper library for local and remote execution environments that contains a set of optimizations such as the pWord2vec, pWord2vec_MPI, Wang2vec and the original Word2vec algorithm. Utilizing these optimizations it is possible to achieve an average performance gain of 15x for multicores and 105x for multinodes compared to the original version. there is also a big reduction in the memory footprint compared to the most popular python versions.

关键词： Natural Language processing Word2vec Performance Evaluation

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Lessons learned from comparing C-CUDA and Python-Numba for GPU-Computing 28

Lessons learned from comparing C-CUDA and Python-Numba for G...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Oden, Lena Fernuniv Inst Math & Informat Hagen Germany

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

Python as programming language is increasingly gaining importance, especially in data science, scientific, and parallel programming. It is faster and easier to learn than classical programming languages such as C. However, usability often comes at the cost of performance and applications written in Python are considered to be much slower than applications written in C or FORTRAN. Further, it does not allow the usage of CPUs-besides of pre-compiled libraries. However, the Numba package promises performance similar to C code for compute intensive parts of a Python application and it supports CUDA, which allows the use of GPUs inside a Python application. In this paper we compare the perforinance of iVumba-CUDA and C-CUDA for different kinds of applications. For compute intensive benchmarks, the performance of the Numba version only reaches between 50% and 85% performance of the CCUDA version, despite the reduction operation, where the Numba version outperforms CUDA. Analyzing the PTX code and CUDA performance counters revealed that index-calculation is one 'uniting factor in Numba. Another problem is the type interference for single precision computations, as sonic values are computed in double precision. By optimizing this within the Numba package, the performance of Numba improves. However, C-CUDA applications still outperform the Numba versions. Further analysis with the CloverLeav Mini App shows that Numba performance further decreases for applications with multiple different compute kernels. the non-CPU part slows down these applications, due to the slow Python interpreter. this leads to a worse GPU utilization.

关键词： Python Graphics processing units Libraries Kernel Indexes Benchmark testing

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Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design through Constraint Programming 28

Temperature-Aware Core Mapping for Heterogeneous 3D NoC Desi...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Derniriz, Ayhan Ahangari, Hamzeh Ozturk, Ozcan Gebze Tech Univ TR-41400 Kocaeli Turkey Bilkent Univ TR-06800 Ankara Turkey

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

In the context of network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance and power consuinption. Moreover, in emerging 3D NoC systems, by intensification of cooling issues, temperature constraints on hot-spots are added, and problem becomes more complicated. In this paper, an earlier Constraint Programming (('P) methodology for heterogeneous 2D NoC design is extended to 3D model, while critical temperature constraints are accounted. In a single stage, our approach can choose core types from a set of low, medium and high power, and assign them to appropriate places on the mesh which minimizes the overall computation time and communication cost while satisfying the temperature constraints. To achieve our objective, in addition to cores placement problem, tasks should also be scheduled on corresponding cores with matching performance levels to minimize the overall completion time (makespan). Experimental results show that task completion times are more dependent on the mesh structure for our benchmark data. 3D mesh structures may yield shorter task completion times, without compromising thermal constraints. On the other hand, restricting the peak temperature naturally requires the usage of low-performance computing elements which inherently may delay the processing time.

关键词： network-on-Chip 3D Integration Heterogeneous Core Mapping Task Scheduling Constraint Programming

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