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检索条件"任意字段=11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications"

共 2194 条记录，以下是181-190 订阅

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A Hypervisor for MIPS-based Architecture Processors - a Case Study in Loongson Processors

A Hypervisor for MIPS-based Architecture Processors - a Case...

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15th ieee international conference on High Performance computing and Communications (HPCC) /11th ieee/IFIP international conference on embedded and Ubiquitous computing (EUC)

作者： Zhou, Rui Ai, Zhu Yang, Jiaming Chen, Yucong Li, Jun Zhou, Qingguo Li, Kuan-Ching Lanzhou Univ Sch Informat Sci & Engn Lanzhou 730000 Gansu Peoples R China Providence Univ Dept Comp Sci & Informat Engn CSIE Taichung Taiwan

ISBN: (纸本)9780769550886

Loongson is a family of general purpose processors based on MIPS architecture designed and manufactured in Mainland China. With the maturity of Loongson CPUs, applications are widely available with the increasing development of software tools and hardware platforms by research teams in academia and industry. In recent years, products based on Loongson have been mainly used in education, personal computers and server systems. Meanwhile, it is not yet popularly used in industrial real-time control fields, so such products have large room and potential to further development and deployment. the M-Hypervisor discussed in this paper is a real-time hypervisor designed for MIPS architecture and implemented in Loongson2F processor. It is based on the management program of para-virtualization whilst multiple partitions are scheduled to execute according to their priorities. the design and implementation of M-Hypervisor is discussed, along with details as timer, interrupts, memory management, partition loading and scheduling, to enrich real-time virtualized applications for MIPS architecture. Evaluation results show the performance and viability of proposed design, being promising to new deployments.

关键词： real-time systems hypervisor MIPS Loongson2F processor

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Exploiting Simultaneous Multithreading in Priority-Driven Hard real-time systems 26

Exploiting Simultaneous Multithreading in Priority-Driven Ha...

引用

ieee 26th international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Osborne, Sims Hill Ahmed, Shareef Nandi, Saujas Anderson, James H. Univ North Carolina Dept Comp Sci Chapel Hill NC 27515 USA

ISBN: (纸本)9781728144030

Simultaneous multithreading (SMT) has the ability to dramatically improve real-time scheduling, but existing methods are cumbersome, frequently need specialized hardware, or are limited to producing table-based schedules. Here, an easily portable method for quickly applying SMT to priority-driven hard real-time systems is given. Using a combination of integer linear programming and heuristic binpacking, a partitioned earliest-deadline-first (EDF) scheduler that takes advantage of SMT is produced. the integer linear programming and partitioning are done offline, but generally require only a few seconds, even given over a hundred tasks. A large-scale schedulability study is conducted, showing that compared to partitioned scheduling without SMT, the schedulable utilization for the considered hardware platform is nearly doubled in the best cases.

关键词： real-time systems simultaneous multi-threading hard real-time scheduling algorithms

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Simulation Environment for time-Triggered Ethernet

Simulation Environment for Time-Triggered Ethernet

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11th ieee international conference on Industrial Informatics (INDIN)

作者： Abuteir, Mohammed Obermaisser, Roman Univ Siegen D-57068 Siegen Germany

ISBN: (纸本)9781479907526

time-Triggered Ethernet (TTEthernet) is an SAE standard of a real-time Ethernet extension, which supports real-time requirements, fault isolation and mixed criticality applications. TTEthernet supports different communication mechanisms ranging from best-effort messaging with a high channel utilization to predictable real-time messaging based on a time-triggered communication schedule. this paper presents a simulation framework for TTEthernet-based systems, which supports the analysis and validation of TTEthernet-based applications at early development stages. We introduce generic model building blocks (e. g., TTEthernet switches, TTEthernet end systems, fault injectors), which can be instantiated, configured and extended to model distributed embedded applications. In particular, these building blocks can be configured to support application-specific time-triggered schedules and communication topologies. the fault injector allows to evaluate the reliability in the presence of messages failures with given failure modes and failure rates. We demonstrate the simulation environment in an example scenario with two TTEthernet switches, multiple end systems and injected faults.

关键词： embedded systems failure analysis local area networks telecommunication network topology

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On-line thermal-aware Task Management for three-dimensional Dynamically Partially Reconfigurable systems

On-line Thermal-aware Task Management for Three-dimensional ...

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ieee 19th international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Wang, Yen-Wen Chen, Ya-Shu Natl Taiwan Univ Sci & Technol Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9781479908509

thermal management is a major design challenge in three-dimensional dynamically partially reconfigurable systems. Unlike three-dimensional integrated circuits, thermal management is more difficult in three-dimensional dynamically partially reconfigurable systems because of the extra heat generated by task reconfiguration. this study proposes an on-line thermal-aware task management scheme to reclaim the run-time thermal slack from lowpower tasks, and uses a configurable thermal threshold to achieve a trade-off between the reconfiguration overhead and thermal distribution. the proposed scheme maximizes the tolerable task execution power to better utilize the system and provides a quality of service guarantee under the thermal constraint. this study also evaluates the capability of the proposed methodology using a series of experiments, presenting encouraging results.

关键词： 3D field programmable gate arrays FPGA dynamic partial reconfiguration task management thermal management

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An Extensible Framework for real-time Task Generation and Simulation

An Extensible Framework for Real-time Task Generation and Si...

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1st international Workshop on Cyber-Physical systems, Networks, and applications (CPSNA) held during 17th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Belwal, Chaitanya Cheng, Albert M. K. Univ Houston Dept Comp Sci Houston TX 77004 USA

ISBN: (纸本)9780769545028

In real-time systems research, validations are usually performed by executing synthetically generated tasks through programmatic implementations of derived algorithms or theoretical results. For every new result, real-time researchers have to develop systems, several times from scratch, for generating task sets as well as implementing their derivations. Another issue arises when the results are submitted for peer review. Reviewers only have access to results in the form of numerical values given in the paper, and have no easy way of validating the results themselves. To solve these two issues, we present a new extensible system for real-time task generation and simulation. Using modern software engineering principles of object and reflection-oriented programming, we show how real-time analysis can be partitioned into sub-systems, where each such subsystem can be implemented as a run-time 'plug-in' which can be independently developed by different research groups. this technique is intended to save real-time researchers the significant amount of time spent in result validation, as well as allow reviewers easy access to the experimental setup of the submitted paper for a more efficient review process.

关键词： Interface Classes real-time Simulation real-time systems Response time Analysis Task Generation real-time systems real-time simulation time series analysis EXPANDABLE simulating SUB-SYSTEM real-time analysis numerical value

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Bounding the Maximum Length of Non-Preemptive Regions Under Fixed Priority Scheduling

Bounding the Maximum Length of Non-Preemptive Regions Under ...

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15th ieee international conference on embedded and real-time computing systems and applications

作者： Yao, Gang Buttazzo, Giorgio Bertogna, Marko Scuola Super Sant Anna Pisa Italy

ISBN: (纸本)9780769537870

the question whether preemptive systems are better than non-preemptive systems has been debated for a long time, but only partial answers have been provided in the real-time literature and still some issues remain open. In filet, each approach has advantages and disadvantages, and no one dominates the other when both predictability and efficiency have to be taken into account in the system design. In particular;limiting preemptions allows increasing program locality, making timing analysis more predictable with respect to the Ally preemptive case. In this paper we integrate the features of both preemptive and non-preemptive scheduling by considering that each task can switch to non-preemptive mode, at any time, for a bounded interval. three methods (with different complexity and performance) are presented to calculate the longest non-preemptive interval that can be executed by each task, under fixed priorities, without degrading the schedulability of the task set, with respect to the fully preemptive case. the methods are also compared by simulations to evaluate their effectiveness in reducing the number of preemptions.

关键词： real time systems

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Optimal Assignment of real-time systems into Multi-context Dynamically Reconfigurable Processors

Optimal Assignment of Real-time Systems into Multi-context D...

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15th ieee international conference on embedded and real-time computing systems and applications

作者： Kitani, Tomoya Nakahashi, Ryo El-Fakih, Khaled Higashino, Teruo Shizuoka Univ Shizuoka 4228529 Japan Osaka Univ Suita Osaka 565 Japan Amer Univ Washington DC 20016 USA

ISBN: (纸本)9780769537870

In this paper, we focus on the problem of implementing a periodic concurrent system with timing constraints into multi-context dynamically reconfigurable processors (DRP). A concurrent system has multiple tasks that can be executed in parallel. Moreover, some tasks in a specific set of processes might be required to synchronize each other. We propose a method for assigning tasks into a multi-context DRP such that timing constraints of the system are satisfied and the size of the program area required on each context for implementing the given system is minimized. We formulate the problem as an ILP problem and propose a heuristic algorithm for solving the ILP problem efficiently. Experimental results and a case study using ubiquitous sensor devices arc given.

关键词： task assignment multi-context dynamically reconfigurable processor ILP formulation heuristic approach

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Psychological Effects on Positional Relationships Between a Person and a Human-Following Robot 24

Psychological Effects on Positional Relationships Between a ...

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24th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Maehara, Keita Fujinami, Kaori Tokyo Univ Agr & Technol Dept Comp & Informat Sci Koganei Tokyo Japan

ISBN: (纸本)9781538677599

A person-following robot must understand the psychological effects of a user to maintain a good relationship with them. In this paper, we define factors that affect the user's psychological states by factor analysis. Also, we present an overall score of the following effect for various following positions based on user evaluation. the result shows that a higher score is obtained if the robot follows close and is beside the person than that if the robot follows the person from a distance.

关键词： Robot sensing systems Psychology Mobile robots Position measurement Standards Face

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Agnostic Hardware-Accelerated Operating System for Low-End IoT 28

Agnostic Hardware-Accelerated Operating System for Low-End I...

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28th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Silva, Miguel Gomes, Tiago Pinto, Sandro Univ Minho Ctr ALGORITMI Braga Portugal

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

there is increasing pressure to optimize Internet of things (IoT) low-end devices. the ever-growing number of requirements and constraints is pushing towards maximizing performance and real-time, but simultaneously minimizing power consumption, form factor, and memory footprint. this has motivated the adoption of Field-Programmable Gate Array (FPGA) technology to accelerate computing-intensive workloads in hardware. However, and despite the ongoing trend of migrating application-level tasks to hardware, recently, the offload of system software such as operating system (OS) services has received little attention. this paper presents CHAMELIoT, a framework for FPGA-based IoT platforms that provides agnostic hardware acceleration to OS services by leveraging RISC-V technology. CHAMELIoT allows for developers to run unmodified applications in a set of well-established IoT OSes. Currently, the framework has support for RIOT, Zephyr, and FreeRTOS. the evaluation showed that latency and determinism can be enhanced up to 10x while the system's performance can be increased to nearly 200%. CHAMELIoT will be open-sourced.

关键词： Performance evaluation Power demand Operating systems Memory management Jitter Market research real-time systems

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Hypervisor-Induced Negative Interference in Virtualized Multi-Core Platforms: the P4080 Case 11

Hypervisor-Induced Negative Interference in Virtualized Mult...

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11th ieee international Symposium on embedded Multicore/Many-Core systems-on-Chip (MCSoC)

作者： Dutta, Sourav Kagaris, Dimitri Ramaprasad, Harini Southern Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA Univ N Carolina Dept Comp Sci Charlotte NC USA

ISBN: (纸本)9781538634417

Modern real-time (RT) applications heavily depend on multi-core processors to meet the increasing computing demands within strict time-constraints. To reduce the cost of overall hardware, most of these applications run along with general purpose workloads on the same hardware platform which may create data contention in shared resources and incur delay for the time critical RT applications. Virtualization of the hardware platform under the supervision of a Virtual Machine Monitor (VMM) or hypervisor allows the isolation of shared resources among concurrent applications from different domains. However, the actual partitioning of hardware resources among the hosted operating systems as well as the hypervisor play a significant role in the performance of the RT applications. In this paper we report results of an experimental investigation for this purpose on a particular multi-core platform, the P4080 developed by Freescale Semiconductor Inc. Using the actual (not simulated) P4080 hardware platform and the Topaz hypervisor, we examined the effect that the partition of the last-level cache (LLC) among a real-time Operating System (RTOS), a General Purpose Operating System (GPOS) and the hypervisor has on the performance of the RT tasks. We have identified inverted bell-shaped curves that seem to govern the optimal allocation of resources for P4080.

关键词： Virtual machine monitors Hardware Operating systems Interference Task analysis time factors real-time systems Virtual machine monitors Operating systems task analysis time Factors real-time systems Hardware Platform Computer hardware Resource utilization general purpose operating system interference Room temperature centromere interference

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