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DeepPicarMicro: Applying TinyML to Autonomous Cyber Physical systems 28

DeepPicarMicro: Applying TinyML to Autonomous Cyber Physical...

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28th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Bechtel, Michael Weng, QiTao Yun, Heechul Univ Kansas Lawrence KS 66045 USA

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

Running deep neural networks (DNNs) on tiny Micro-controller Units (MCUs) is challenging due to their limitations in computing, memory, and storage capacity. Fortunately, recent advances in both MCU hardware and machine learning software frameworks make it possible to run fairly complex neural networks on modern MCUs, resulting in a new field of study widely known as TinyML. However, there have been few studies to show the potential for TinyML applications in cyber physical systems (CPS). In this paper, we present DeepPicarMicro, a small self-driving RC car testbed, which runs a convolutional neural network (CNN) on a Raspberry Pi Pico MCU. We apply a state-of-the-art DNN optimization to successfully fit the well-known PilotNet CNN architecture, which was used to drive NVIDIA's real self-driving car, on the MCU. We apply a state-of-art network architecture search (NAS) approach to find further optimized networks that can effectively control the car in real-time in an end-to-end manner. From an extensive systematic experimental evaluation study, we observe an interesting relationship between the accuracy, latency, and control performance of a system. From this, we propose a joint optimization strategy that takes both accuracy and latency of a model in the network architecture search process for AI enabled CPS.

关键词： real-time Autonomous Car Convolutional Neural Network Microcontroller Case Study TinyML

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Performance Isolation for real-time systems with Xen Hypervisor on Multi-cores 20

Performance Isolation for Real-time Systems with Xen Hypervi...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Jing, Wei Guan, Nan Yi, Wang Hatteland Display AS Stavanger Norway Northeastern Univ Beijing Peoples R China Uppsala Univ Uppsala Sweden

ISBN: (纸本)9781479939534

Virtualization techniques are gaining significant interests in embedded real-time system design. However, existing virtualization platforms lack strong performance isolation among virtual machines. In this work we propose a method to monitor and control the shared memory accesses of individual virtual machines on multi-core processors with Xen hypervisor, to enhance the performance isolation among virtual machines and improve the timing predictability of real-time applications. Experiments with the SPEC2006 benchmark programs are conducted to validate the proposed method.

关键词： Virtual machine

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Task Migration for Energy Saving in real-time Multiprocessor systems 16

Task Migration for Energy Saving in Real-Time Multiprocessor...

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16th ieee Int Conf on High Performance computing and Communications/11th ieee Int Conf on embedded Software and systems\6th Int Symposium on Cyberspace Safety and Security

作者： Zeng, Gang Matsubara, Yutaka Tomiyama, Hiroyuki Takada, Hiroaki Nagoya Univ Grad Sch Engn Chikusa Ku Furo Cho Nagoya Aichi 4648603 Japan Nagoya Univ Grad Sch Informat Sci Chikusa Ku Nagoya Aichi 4648603 Japan Ritsumeikan Univ Coll Sci & Engn Kusatsu Shiga 5258577 Japan

ISBN: (纸本)9781479961238

A task migration method is proposed for energy savings in multiprocessor real-time systems. the method is based on the portioned scheduling technique which classifies each task into a fixed task or a migratable task. the energy-aware migration with specified parameters is formulated as a linear programming problem, and optimal solution is given. Furthermore, the method is extended to more general case with a complete migration algorithm. Simulation results showed significant energy savings over existing methods.

关键词： real-time systems Energy Optimization Multiprocessor Task migration Dynamic Voltage Scaling

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Energy-Adaptive real-time Sensing for Batteryless Devices 28

Energy-Adaptive Real-time Sensing for Batteryless Devices

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28th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Karimi, Mohsen Wang, Yidi Kim, Hyoseung Univ Calif Riverside Riverside CA 92521 USA

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

the use of batteryless energy harvesting devices has been recognized as a promising solution for their low maintenance requirements and ability to work in harsh environments. However, these devices have to harvest energy from ambient energy sources and execute real-time sensing tasks periodically while satisfying data freshness constraints, which is especially challenging as the energy sources are often unreliable and intermittent. In this paper, we develop an energy-adaptive real-time sensing framework for batteryless devices. this framework includes a lightweight machine learning-based energy predictor that is capable of running on microcontroller devices and predicting the energy availability and intensity based on energy traces. Using this, the framework adapts the schedule of real-time tasks by effectively taking into account the predicted energy supply and the resulting age of information of each task, in order to achieve continuous sensing operations and satisfy given data freshness requirements. We discuss various design choices for adaptive scheduling and evaluate their performance in the context of batteryless devices. Experimental results show that the proposed adaptive real-time approach outperforms the recent methods based on static and reactive approaches, in both energy utilization and data freshness.

关键词： Performance evaluation Schedules Runtime Microcontrollers Data integrity Solar energy real-time systems

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IPDeN: real-time deflection-based NoC with in-order flits delivery 28

IPDeN: Real-Time deflection-based NoC with in-order flits de...

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28th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Gonzalez, Yilian Ribot Nelissen, Geoffrey Tovar, Eduardo Polytech Inst Porto ISEP CISTER Res Ctr Porto Portugal Eindhoven Univ Technol Eindhoven Netherlands

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

In deflection-based Network-on-Chips (NoC), when several flits entering a router contend for the same output port, one of the flit is routed to the desired output and the others are deflected to alternatives outputs. the approach reduces power consumption and silicon footprint in comparison to virtual-channels (VCs) based solutions. However, due to the non-deterministic number of deflections that flits may suffer while traversing the network, flits may be received in an out-of-order fashion at their destinations. In this work, we present IPDeN, a novel deflection-based NoC that ensures in-order flit delivery. To avoid the use of costly reordering mechanisms at the destination of each communication flow, we propose a solution based on a single small buffer added to each router to prevents flits from over taking other flits belonging to the same communication flow. We also develop a worst-case traversal time (WCTT) analysis for packets transmitted over IPDeN. We implemented IPDeN in Verilog and synthesized it for an FPGA platform. We show that a router of IPDeN requires approximate to 3-times less hardware resources than routers that use VCs. Experimental results shown that the worst-case and average packets communication time is reduced in comparison to the state-of-the-art.

关键词： real-time embedded systems systems-on-Chips Network-on-Chips Worst-Case Traversal time

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Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms 26

Contending memory in heterogeneous SoCs: Evolution in NVIDIA...

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ieee 26th international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Capodieci, Nicola Cavicchioli, Roberto Olmedo, Ignacio Sanudo Solieri, Marco Bertogna, Marko Univ Modena & Reggio Emilia Modena Italy

ISBN: (纸本)9781728144030

Modern embedded platforms are known to be constrained by size, weight and power (SWaP) requirements. In such contexts, achieving the desired performance-per-watt target calls for increasing the number of processors rather than ramping up their voltage and frequency. Hence, generation after generation, modern heterogeneous System on Chips (SoC) present a higher number of cores within their CPU complexes as well as a wider variety of accelerators that leverages massively parallel compute architectures. Previous literature demonstrated that while increasing parallelism is theoretically optimal for improving on average performance, shared memory hierarchies (i.e. caches and system DRAM) act as a bottleneck by exposing the platform processors to severe contention on memory accesses, hence dramatically impacting performance and timing predictability. In this work we characterize how subsequent generations of embedded platforms from the NVIDIA Tegra family balanced the increasing parallelism of each platform's processors with the consequent higher potential on memory interference. We also present an open-source software for generating test scenarios aimed at measuring memory contention in highly heterogeneous SoCs.

关键词： Memory Interference GP-GPU Compute Accelerators real-time Tegra

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A Concurrency Framework for Priority-Aware Intercomponent Requests in CAmkES on seL4 28

A Concurrency Framework for Priority-Aware Intercomponent Re...

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28th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Sudvarg, Marion Gill, Chris Washington Univ Dept Comp Sci & Engn St Louis MO 63110 USA

ISBN: (数字)9781665453448

ISBN: (纸本)9781665453448

Component-based design can encapsulate and isolate state and the operations on it, but timing semantics crosscut these boundaries when a real-time task's control flow spans multiple components. Under priority-based scheduling, intercomponent control flow should be coupled with priority information, so that task execution can be prioritized appropriately end-to-end. However, the CAmkES component architecture for the seL4 microkernel does not adequately support priority propagation across intercomponent requests: component interfaces are bound to threads that execute at fixed priorities provided at compile-time in the component specification. In this paper, we present a new library for CAmkES with a thread model that supports (1) multiple concurrent requests to the same component endpoint;(2) propagation and enforcement of priority metadata, such that those requests are appropriately prioritized;and (3) implementations of Non-Preemptive Critical Sections, the Immediate Priority Ceiling Protocol and the Priority Inheritance Protocol for components encapsulating critical sections of exclusive access to a shared resource. We measure overheads and blocking times for these new features and use existing theory to perform schedulability analysis. Evaluations on both Intel x86 and ARM platforms show that our new library allows CAmkES to provide suitable end-to-end timing for real-time systems.

关键词： Concurrent computing Component architectures Protocols Program processors Semantics Metadata real-time systems

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Dynamic Activation Timing Configuration for Product Line Development

Dynamic Activation Timing Configuration for Product Line Dev...

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1st international Workshop on Cyber-Physical systems, Networks, and applications (CPSNA) held during 17th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Ishigooka, Tasuku Narisawa, Fumio Hitachi Ltd Hitachi Res Lab Ibaraki Japan

ISBN: (纸本)9780769545028

Most automotive control systems have been developed by combining legacy Electronic Control Units (ECUs) with newly developed ECUs. We need to plan the product line to utilize as many legacy ECUs as possible to lower development costs of new vehicles. However, we must develop several new gateway ECUs per new vehicle because gateway ECUs depend on the placement of other ECUs and their combinations within the whole system. the reusable gateway ECUs are needed to lower development cost. However, there is a problem in that the worst case execution time (WCET) of relay processing may be impaired in typical methods that are synchronized with the communication cycle of time-triggered networks. therefore, we propose a Dynamic Activation Timing Configuration (DATC) for product line development, which can dynamically calculate the activation timing of relay processing from the information on message routing, slot assignment, and time-triggered network. the gateway ECUs with DATC can be dynamically adjusted to new vehicles and improve the WCET of relay processing.

关键词： Automotive engineering Dynamic Configuration Event-Triggered Network Gateway Logic gates Relays Routing time-Triggered Network Timing Vehicles automobiles automotive control systems automotive electronics dynamic activation timing configuration electronic control units product development product line development relay processing time-triggered networks worst case execution time

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Multi-ASIP Platform Synthesis for Event-Triggered applications with Cost/Performance Trade-offs

Multi-ASIP Platform Synthesis for Event-Triggered Applicatio...

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ieee 19th international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Gangadharan, Deepak Micconi, Laura Pop, Paul Madsen, Jan Tech Univ Denmark DTU Compute Odense Denmark

ISBN: (纸本)9781479908516

In this paper, we propose a technique to synthesize a cost-efficient distributed platform consisting of multiple Application Specific Instruction Set Processors (multi-ASIPs) running applications with strict timing constraints. Multi-ASIP platform synthesis is a non-trivial task for two reasons. Firstly, we need to know the WCET of tasks in target applications to derive platforms (including synthesized ASIPs) in which the tasks are schedulable. However, the WCET of tasks can be known only after the ASIPs are synthesized. We break this circular dependency by using a probability distribution of the WCET of a task (further referred to as the WCET uncertainty model), which takes into account the underlying microarchitectural configurations for the ASIP implementation. Secondly, the datapath area of the multi-ASIPs synthesized is an important design factor that contributes significantly towards the overall cost of the platform. We propose an area estimation model and a WCET uncertainty model that consider the effect of task datapath similarity. Based on these two models, we support the designer in exploring cost/performance trade-offs during the platform synthesis. We propose an Evolutionary Algorithm-based approach to solve this multiobjective optimization problem. the proposed approach has been evaluated using several benchmarks and it provides a number of multi-ASIP platform solutions exploring the trade-offs in the cost/performance design space.

关键词： Costs

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Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage

Feature Selection and Activity Recognition to Detect Water W...

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作者： Trang thuy Vu Sokan, Akifumi Nakajo, Hironori Fujinami, Kaori Suutala, Jaakko Siirtola, Pekka Alasalmi, Tuomo Pitkanen, Ari Roning, Juha Tokyo Unvers Agr & Technol Dept Comp & Informat Sci Tokyo Japan Univ Oulu Dept Elect & Informat Engn Oulu Finland

ISBN: (纸本)9780769545028

In this paper, water tap usage is examined based on water sound analysis. We focus on detecting "water waste" to make persuasion of water savings effective, where two types of water waste are defined: inter-activity water waste and intra-activity water waste. Based on a preliminary user survey, four types of basin-related activities are identified that occur with water waste. We apply a spectrum subtraction method for feature selection and propose cascaded classifiers for activity recognition. the result of an evaluation presents that the aggregate accuracies to identify inter-activity water waste and intra-activity one are 100.0 % and 81.1 %, respectively.

关键词： Accuracy Error analysis Microphones Monitoring real time systems Sensors Water conservation activity recognition environmental science computing feature selection inter-activity water waste intra-activity water waste learning (artificial intelligence) pattern classification spectrum subtraction method wastewater water sound analysis water tap usage water waste detection

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