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检索条件"任意字段=11th International Conference on Embedded and Real-Time Computing Systems and Applications"

共 3210 条记录，以下是2801-2810 订阅

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Developing embedded Kernel for System-On-a-Chip Platform of Heterogeneous Multiprocessor Architecture

Developing Embedded Kernel for System-On-a-Chip Platform of ...

引用

IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Jing Chen Jian-Hong Liu Department of Electrical Engineering National Cheng Kung University Tainan Taiwan

It has been common that modern embedded system products are built on platforms with system-on-a-chip (SOC) in which two or more different processor cores are put into one single chip and form the architecture of heterogeneous multiprocessor. Although providing high performance at low cost, such architecture brings new design challenges as well as increased complexity in developing embedded software especially at the level of kernel or operating system software. this paper presents our experience in developing an embedded microkernel that runs on embedded system of heterogeneous multiprocessor architecture composed of one general purpose processor (GPP) and one special purpose processor (SPP). Aside from following the traditional approach of monolithic operating system, the option of dual kernels based on microkernel architecture with uniform message-passing mechanism was taken to develop a symmetric embedded microkernel which can be compiled to run separately on each of the different processor cores in the system. the design and the approach not only reduce the software complexity in developing a kernel to manage different processors in a system but also enable a symmetric view from processors of different architectures. A prototype kernel was implemented on a reference design of Texas Instrument's TMS320DSC25 which is a heterogeneous multiprocessor SOC with a GPP of ARM7TDMI core and an SPP of C5409 DSP core

关键词： Kernel System-on-a-chip Computer architecture embedded system embedded software Operating systems Costs Software performance Software systems Software development management

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Deterministic Mechanism for Run-time Reconfiguration Activities in an RTOS

Deterministic Mechanism for Run-time Reconfiguration Activit...

引用

IEEE international conference on Industrial Informatics (INDIN)

作者： Marcelo Gotz Florian Dittmann Carlos Eduardo Pereira Heinz Nixdorf Institute University of Paderborn Germany Electrical Engineering Department UFRGS Brazil

Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of today's embedded systems. However, the relative high reconfiguration costs often are an obstacle when using such architectures for run-time reconfigurable systems. In order to still be able to benefit from the flexibility of such systems, the used real-time operating system must explicitly respect the reconfiguration time. In such systems, the reconfiguration activities need to be carried out during run-time without causing critical applications to miss their deadlines. In this paper, we show how we model these reconfiguration activities as aperiodic jobs. therefore, we apply the server-based method from the real-time scheduling theory to the scheduling of aperiodic activities. Using these techniques, we can achieve a deterministic environment for reconfiguration activities as well as an improvement of their responsiveness.

关键词： Runtime embedded computing High performance computing Computer architecture Field programmable gate arrays embedded system Costs real time systems Operating systems Delay

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Instruction Scheduling with Release times and Deadlines on ILP Processors

Instruction Scheduling with Release Times and Deadlines on I...

引用

IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hui Wu J. Jaffar Jingling Xue School of Computer Science and Engineering University of New South Wales Australia School of Computing National University of Singapore Singapore

ILP (instruction level parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimising compiler for ILP processors needs to find a feasible schedule for a set of time-constrained instructions. In this paper, we present a fast algorithm for scheduling instructions with precedence-latency constraints, individual integer release times and deadlines on an ILP processor with multiple functional units. the time complexity of our algorithm is O(n 2 logd)+min{O(de), O(ne)}+min{O(ne), O(n 2.376 )}, where n is the number of instructions, e is the number of edges in the precedence graph and d is the maximum latency. Our algorithm is guaranteed to find a feasible schedule whenever one exists in the following special cases: 1) one functional unit, arbitrary precedence constraints, latencies in {0,1}, integer release times and deadlines; 2) two identical functional units, arbitrary precedence constraints, latencies of 0, integer release times and deadlines; 3) multiple identical functional units or multiple functional units of different types, monotone interval-ordered graph, integer release times and deadlines; 4) multiple identical functional units, in-forest, equal latencies, integer release times and deadlines. In case 1) our algorithm improves the existing fastest algorithm from O(n 2 logn)+min{O(ne), O(n 2.376 )} to min{O(ne), O(n 2.376 )}. In case 2) our algorithm improves the existing fastest algorithm from O(ne+n 2 logn) to min{O(ne), O(n 2.376 )}. In case 3) no polynomial time algorithm for multiple functional units of different types was known before

关键词： Processor scheduling Delay Scheduling algorithm embedded system Timing Computer science Computer aided instruction embedded computing Optimizing compilers Polynomials

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Integrating timed automata into tabu algorithm for HW-SW partitioning

Integrating timed automata into tabu algorithm for HW-SW par...

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IEEE international conference on Engineering of Complex Computer systems

作者： Geguang Pu Zhang Chong Zongyan Qiu Jifeng He Wang Yi Software Engineering Institute East China Jiao Tong University Shanghai China LMAM and Department of Informatics School of Mathematical Sciences Peking University Beijing China Department of Computer Systems University of Uppsala Sweden

Hardware/software (HW-SW) partitioning is a key problem in codesign of embedded systems, studied extensively in the past. this paper describes a new approach to hardware/software partitioning for synchronous model. We formalize the partitioning problem using timed automata, which captures the key elements of the partitioning. then the tabu algorithm is applied to timed automata model to search for the solution efficiently. An industrial experiment is conducted to show our approach can handle large applications with hundreds of nodes in task graph effectively

关键词： Automata Partitioning algorithms Hardware Application software Cost function Software quality Heuristic algorithms Software engineering Informatics embedded computing

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Resource virtualization in real-time CORBA middleware

Resource virtualization in real-time CORBA middleware

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Christopher D. Gill Department of Computer Science and Engineering Washington University Saint Louis MO USA

Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered. this paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices.

关键词： Resource virtualization Middleware real time systems Application virtualization Distributed computing Concurrent computing embedded system Programming profession Application software Computer architecture

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Integrating Compiler and System Toolkit Flow for embedded VLIW DSP Processors

Integrating Compiler and System Toolkit Flow for Embedded VL...

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IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Chi Wu Kun-Yuan Hsieh Yung-Chia Lin Chung-Ju Wu Wen-Li Shih S. C. Chen Chung-Kai Chen Chien-Ching Huang Yi-Ping You Jenq Kuen Lee Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. this creates challenges to deploy software toolkits for new embedded DSP processors. this article presents our methods and experiences to develop software and toolkit flows for PAC (parallel architecture core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger and DSP micro-kernels. We first retarget open research compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assembler are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dual-core environments. the footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations

关键词： VLIW Digital signal processing Registers Encoding Software tools Assembly Application software embedded software Parallel architectures Pipelines

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the pipeline decomposition tree:: an analysis tool for multiprocessor implementation of image processing applications

The pipeline decomposition tree:: an analysis tool for multi...

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international conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Shuvra S. Bhattacharyya Dong-Ik Ko Department of Electrical and Computer Engineering Institute for Advanced Computer Studies University of Maryland College Park USA

Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. this paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints.

关键词： Pipelines Image analysis Image processing Processor scheduling Application software embedded system Parallel processing Space exploration Multidimensional signal processing embedded computing

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Monocular Vision Based SLAM for Mobile Robots

Monocular Vision Based SLAM for Mobile Robots

引用

international conference on Pattern Recognition

作者： E. Mouragnon M. Lhuillier M. Dhome F. Dekeyser P. Sayd Image and embedded computer Laboratory CEA/LIST/DTSI/SARC Gif-sur-Yvette France LASMEA UMR 6602 du CNRS Université Blaise Pascal Aubiere France

this paper describes a new vision based method for the simultaneous localization and mapping of mobile robots. the only data used is a video input from a moving calibrated monocular camera. From the detection and matching of interest points in images at video rate, robust estimates of the camera poses are computed in real-time and a 3D map of the environment is reconstructed. the computed 3D structure is constantly refined thanks to the introduction of a fast and local bundle adjustment method that makes this approach particularly accurate and reliable. Actually, this method can be seen as a new visual tool that may be used in conjunction with usual systems (GPS, inertia sensors, etc) in SLAM applications

关键词： Simultaneous localization and mapping Mobile robots Cameras Robot vision systems Robustness Optimization methods Image reconstruction Uncertainty Computer vision embedded computing

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Heterogeneous Parallel computing in Remote Sensing applications: Current Trends and Future Perspectives

Heterogeneous Parallel Computing in Remote Sensing Applicati...

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IEEE international conference on Cluster computing

作者： Antonio J. Plaza Computer Science Department University of Extremadura Caceres Spain

Heterogeneous networks of computers have rapidly become a very promising commodity computing solution, expected to play a major role in the design of high performance computing systems for remote sensing missions. Currently, only a few parallel processing strategies are available in this research area, and most of them assume homogeneity in the underlying computing platform. this paper develops several highly innovative heterogeneous parallel algorithms for information extraction from high-dimensional remotely sensed images, with particular emphasis on target detection and land-cover mapping applications. Experimental results are presented in the context of a realistic application, using real data collected by NASA's Jet Propulsion Laboratory over the World Trade Center complex in New York City after September 11th, 2001. Parallel performance of the proposed algorithms is discussed using several (fully and partially) heterogeneous networks at University of Maryland, and a massively parallel Beowulf cluster at NASA's Goddard Space Flight Center. Combined, these parts deliver a snapshot of the state-of-the-art in those areas, and a thoughtful perspective on the potential and challenges of applying heterogeneous computing practices to remote sensing problems

关键词： Parallel processing Remote sensing High performance computing Computer networks Application software Concurrent computing Parallel algorithms Data mining Object detection Propulsion

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A nano operating system for wireless sensor networks

A nano operating system for wireless sensor networks

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international conference on Advanced Communication Technology (ICACT)

作者： Seungmin Park Jin Won Kim Kee-Young Shin Daeyoung Kim Ubiquitous Computing Middleware research Team Embedded Software Research Division Electronics and Telecommnications Research Institute Daejeon South Korea Division of Information and Communication Engineering CNU Daejeon South Korea

In recent years, the availability of cheap and small micro sensor node and low power wireless communication give a contribution of enhanced developments of wireless sensor network application in real society. Furthermore, middlewares and operating systems for convenience on development of sensor network application are essentially needed. In this paper, we introduce a sensor network operation system, Nano-Qplus platform, which is flexible, dynamic, and easy manageable for sensor network application programmer. Furthermore, for the purpose of performance evaluation, we compare Nano-Qplus to other sensor network operating systems related to memory read/write time and task creation latency. the results of performance analysis shows that Nano-Qplus offers enhanced advantages that other sensor network operating systems, so we can notice Nano-Qplus is easily applied to real sensor network application

关键词： Operating systems Wireless sensor networks Sensor systems and applications Network operating systems Wireless communication Middleware Programming profession Sensor systems Read-write memory Delay

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