Advances in multimedia computing offer new approaches to support on-line access to information from a variety of sources such as video, audio, images, and transparencies. the key to success in providing distributed re...
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Advances in multimedia computing offer new approaches to support on-line access to information from a variety of sources such as video, audio, images, and transparencies. the key to success in providing distributed real-time retrieval, is the control of network delay and congestion to keep up the desired quality-of-service (QoS). In this paper we present a new distributed multimedia database environment, called NetMedia. this environment can support controlled delivery of video, audio, and text data, across Internet. NetMedia can be the base of various distributed multimedia applications. As an example we present NetMedia-Virtual-Classroom, an asynchronous distance learning tool, which uses the advantages of the NetMedia framework.
To overcome the difficulties of computation-intensive multimedia applications, the development groups of major CPU manufactories, such as Intel and Digital, have decided to include new instruction sets into their CPU ...
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To overcome the difficulties of computation-intensive multimedia applications, the development groups of major CPU manufactories, such as Intel and Digital, have decided to include new instruction sets into their CPU families to increase their multimedia handling ability. the newly introduced instruction set is basically in a Single Instruction Multiple Data (SIMD) Stream operation type. For the practical purpose (e.g. the trade off between the complexity of hardware implementation and the so-obtained performance improvement), they use a reduced SIMD instruction set instead of the full one. Taking Intel as an example, the new instruction set is composed of 57 operations called the Multimedia eXtension (MMX) instruction set. Nowadays, how to fully utilize the power of the embedded instruction set for providing various multimedia applications becomes an interesting and important issue. In this paper, we demonstrate an efficient realization, based on the new MMX instruction set, of the block Inverse Discrete Cosine Transform (IDCT) and Motion Compensation (MC) which are kernel components of the block-based decoding standards, such as MPEG-1, MPEG-2, H.261 and H.263. the convincing results show that: withthe add of proper SIMD instruction set, the pure software solution for complicated multimedia applications such as real-time MPEG video decoding) becomes feasible.
PROFIBUS, being a national German (DIN 19245) and an European (EN 50170) standard, has become the most widely accepted modern fieldbus technology in Europe. It is expected to take a similar role on the world market, s...
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PROFIBUS, being a national German (DIN 19245) and an European (EN 50170) standard, has become the most widely accepted modern fieldbus technology in Europe. It is expected to take a similar role on the world market, since the IEC standardisation efforts for a common international fieldbus failed recently. A major reason for its success is the technological and functional scalability based on a common core. Now, a wide range of PLCs as well as low cost process I/O is available (also from leading manufacturers like Siemens) which enable easy interfacing. ZEL, the central electronics facility of Forschungszentrum Julich, has decided to use predominantly industrial components (PLCs, I/Os, etc.) in the front end of slow control systems for physics experiments.
Tokamak magnetic fusion research has progressed to an advanced project, i.e., ITER (internationalthermonuclear Experimental Reactor). therefore, existing tokamaks must explore operational scenarios necessary for a hi...
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Tokamak magnetic fusion research has progressed to an advanced project, i.e., ITER (internationalthermonuclear Experimental Reactor). therefore, existing tokamaks must explore operational scenarios necessary for a high-performance plasma while simultaneously suppressing any disruptive instabilities. To implement this investigation, various advanced real-time controls using processed profile data and all available actuators should be tested in the experiments. To satisfy these requirements at the large tokamak JT-60, we are upgrading its original real-time control system completely. Two criteria for the new system configuration have been adopted: (i) the distributed processors for the measurements, actuators, and supervisory controllers (SVCs) am linked through a "reflective memory (RM)" network for fast, real-time communication. the profile data in the RM modules are also updated in realtime. (ii) For efficient parallel and pipeline processes performed by multiple controllers, synchronization is provided from two sources: external hardware clocks and software counters in the RMS, which are updated by the SVCs. For a control function, the following simple and flexible method has been employed to perform various experimental proposals: New test control methods are first registered in the supervisory controllers. In accordance withthe preprogrammed waveforms that indicate which control method to use, the SVCs select the correct control method in realtime. the upgraded configuration of the JT-60 plasma control system and its effectiveness in seeking advanced operational scenarios applicable to ITER are discussed in detail.
Advances in the computer technology encouraged the avionics industry to replace the federated design of control units with an integrated suite of control modules that share the computing resources. the new approach, w...
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ISBN:
(纸本)081869209X
Advances in the computer technology encouraged the avionics industry to replace the federated design of control units with an integrated suite of control modules that share the computing resources. the new approach, which is called integrated modular avionics (IMA), cart achieve substantial cost reduction in the development, operation and maintenance of airplanes. A set of guidelines has been developed by the avionics industry to facilitate the development and certification of integrated systems. Among them, a software architecture is recommended to address real-time and fault-tolerance requirements. According to the architecture, applications are classified into partitions supervised by an operating system executive. A general-purpose application/executive (APEX) interface is defined which identifies the minimum functionality provided to the application software of an NMA system. To support the temporal partitioning between applications, APEX interface requires a deterministic cyclic scheduling of partitions at the O/S level and a fixed priority scheduling among processes within each partition. In this paper we propose a scheduling scheme for partitions in APEX. the scheme determines the frequency that each partition must be invoked and the assignment of processor capacity on every invocation. then a cyclic schedule at the O/S level can be constructed and all processes within each partition can meet their deadline requirements.
All in all, the experience gained withthe practical application of these research results is promising. the notations proved to be applicable to representative real-world problems, and improvements in terms of precis...
ISBN:
(纸本)3540650709
All in all, the experience gained withthe practical application of these research results is promising. the notations proved to be applicable to representative real-world problems, and improvements in terms of preciseness and degree of automation of the system development could be shown. Nevertheless, the transfer of the approaches crucially depends on the acceptance by the users. this requires comprehensive education and coaching. Furthermore, experiments have to be carried out to prove the real benefit of the use of formal methods in terms of development time and cost over the whole system's life cycle. the result should be a guideline for the specific use of formal methods regarding the system characteristics as well as the safety and reliability requirements of the system and its components.
the proceedings contain 24 papers. the special focus in this conference is on Java, Locality and Network computing. the topics include: From flop to megaflops;considerations in HPJava language design and implementatio...
ISBN:
(纸本)3540664262
the proceedings contain 24 papers. the special focus in this conference is on Java, Locality and Network computing. the topics include: From flop to megaflops;considerations in HPJava language design and implementation;a loop transformation algorithm based on explicit data layout representation for optimizing locality;an integrated framework for compiler-directed cache coherence and data prefetching;I/O granularity transformations;a programming system for emerging scalable interactive multimedia applications;network-aware parallel computing with remos;object-oriented implementation of data-parallelism on global networks;optimized execution of fortran 90 array language on symmetric shared-memory multiprocessors;a retargetable environment for automatic data layout;automatic parallelization of C by means of language transcription;improving compiler and run-time support for irregular reductions using local writes;container-centric approach for parallelization of real-world symbolic applications;a new framework for generating efficient code for sparse matrix computations;HPF-2 support for dynamic sparse computations;integrated instruction scheduling and register allocation techniques;a spill code placement framework for code scheduling;copy elimination for parallelizing compilers;compiling for SIMD within a register;automatic analysis of loops to exploit operator parallelism on reconfigurable systems;principles of speculative run-time parallelization;the advantages of instance-wise reaching definition analyses in array SSA and dependency analysis of recursive data structures using automatic groups.
the proceedings contain 25 papers. the special focus in this conference is on Industrial Issues and Concurrency. the topics include: Industrial requirements for the efficient development of reliable embeddedsystems;t...
ISBN:
(纸本)3540650709
the proceedings contain 25 papers. the special focus in this conference is on Industrial Issues and Concurrency. the topics include: Industrial requirements for the efficient development of reliable embeddedsystems;the specification and refinement of an environmental model;formal derivation of finite state machines for class testing;using B to specify, verify and design hardware circuits;Z on the web using java;visualizing Z notation in HTML documents;on the semantic relation of Z and HOL;designing a requirements specification language for reactive systems;analyzing a real-time program with Z;recursive definitions in Z;a logic for the schema calculus;combining specification techniques for processes, data and time;innovations in the notation of standard Z;comparing extended Z with a heterogeneous notation for reasoning about time and space;inconsistency and undefinedness in Z;compositional specification of controllers for batch process operations;testing refinements by refining tests and pushing the state of the art in industrial refinement.
Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules suck that its real-time and other constraints are met. embeddedsystems ar...
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Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules suck that its real-time and other constraints are met. embeddedsystems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embeddedsystems, the task graphs are usually hierarchical in nature. the embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embeddedsystems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. Our co-synthesis algorithm has the following features: 1) it supports periodic task graphs withreal-time constraints, 2) it supports pipelining of task graphs, 3) it supports a heterogeneous set of PEs and communication links, 4) it allows both sequential and concurrent modes of communication and computation, 5) it employs a combination of preemptive and non-preemptive static scheduling, 6) it employs a new task clustering technique suitable for hierarchical task graphs, and 7) it uses the concept of association arrays to tackle the problem of multi-rate tasks encountered in multimedia systems. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first timethe notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm
the proceedings contain 94 papers. the special focus in this conference is on Spatial, Temporal and Spatio-Temporal Planning and Scheduling. the topics include: Neurocybernetics, codes and computation;the grand challe...
ISBN:
(纸本)3540645748
the proceedings contain 94 papers. the special focus in this conference is on Spatial, Temporal and Spatio-Temporal Planning and Scheduling. the topics include: Neurocybernetics, codes and computation;the grand challenge is called;a progressive heuristic search algorithm for the cutting stock problem;generic csp techniques for the job-shop problem;a fast and efficient solution to the capacity assignment problem using discretized learning automata;using oxsim for path planning;multi-directional search with goal switching for robot path planning;analytical potential fields and control strategies for motion planning;exact geometry and robot motion planning;an evolutionary and local search algorithm for planning two manipulators motion;a genetic algorithm for robust motion planning;coordinated motion of two robot arms for realapplications;a low-risk approach to mobile robot path planning;generating heuristics to control configuration processes;valuing the flexibil1ty of flexible manufacturing systems with fast decision rules;optimal periodic control with environmental application;a centralised hierarchical task scheduler for an urban traffic control system based on a multiagent architecture;a direct iteration method for global dynamic control of redundant manipulators;design of ship-board control system based on the soft computing conception;expert diagnostic using qualitative data and rule-based inferential reasoning and alarm processing and reconfiguration in power distribution systems.
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