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A Low Latency Stochastic Square Root Circuit

A Low Latency Stochastic Square Root Circuit

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international conference on VLSI Design

作者： Shyamali Mitra Debojyoti Banerjee Mrinal K. Naskar Jadavpur University Kolkata India

Stochastic computing (SC) has shown promise over years due to its relative simplicity in hardware design enabling low power compared to conventional computing paradigm. the error tolerance and hardware-efficient solutions of SC have made it extremely popular in a variety of applications like decoding of Low Discrepancy sequences, image processing tasks, etc. In the present work, two architectures of Stochastic Square Root Circuit (SSRC) have been proposed. the first architecture uses different constant-length stochastic numbers (SNs) and calculates the square root in two iterations providing reasonably accurate results throughout the input range. the accuracy is compared with state-of-the-art architectures and significant improvement in the accuracy for a lower range of inputs, i.e. 0-0.2 is noted. Another architecture consists of an accuracy control where the desired accuracy can be decided by a user. Studies are conducted to reveal that, in contrary to the fixed-length bitstream, a progressive increment of bitstream at each iteration utilizes a lesser number of clock cycles to converge to the desired accuracy for higher input range 0.6-1. the proposed SSRC is validated on two standard images for square root based contrast enhancement function to reveal close proximity with the traditional square root based enhanced image compared to other existing SSRCs.

关键词： Image processing Computer architecture Very large scale integration Hardware real-time systems Iterative methods Task analysis

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Configuring an embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge computing applications

Configuring an Embedded Neuromorphic Coprocessor Using a RIS...

引用

IEEE international Symposium on embedded Multicore Socs (MCSoC)

作者： Evelina Forno Andrea Spitale Enrico Macii Gianvito Urgese Politecnico di Torino Torino (TO) ITALY

ISBN: (纸本)9781728187525

Neuromorphic hardware shows promising potential for employment in edge computing applications, as it can provide real-time and low-power elaboration of complex data directly on edge using computational paradigm based on Spiking Neural Networks (SNNs). However, such systems cannot be deployed as edge devices by themselves, as they require an external host for configuration and data input management. In this paper, we present a chip-level integrated system performing on-edge configuration of a neuromorphic platform. the proposed solution makes use of two existing open-source platforms: the low-power RISC-V processor Rocket Chip and the digital SNN processor ODIN. We built the two systems into a single SoC using the Chipyard framework, and connected them by designing a communication interface using ODIN's SPI and AER input/output ports. We validated the system by RTL simulation of a synfire chain running on ODIN, where Rocket Chip sets up configuration of the network, triggers the first spike, then collects the simulation results. the synthesized design utilizes a modest amount of resources on a PYNQ-Z2 board: 16% of LUT slices, 11% of Block RAMs and 8 pins, leaving plenty of room to integrate other peripherals or systems. the present work represents a first step towards seamless integration of neuromorphic technologies with state-of-the-art processors, improving on the ease of use of neuromorphic devices and leading the way into widespread use of SNN coprocessors in edge computing applications.

关键词： Rockets Neuromorphics Simulation Process control Hardware Central Processing Unit Table lookup

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A content-based intelligent mobile video censoring system 7

A content-based intelligent mobile video censoring system

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7th IEEE international conference on Progress in Informatics and computing, PIC 2020

作者： Wang, Jing Yuan, Chenyu Liu, Yao Lin, Yuxuan Liang, Jian City College of Huizhou School of Mechatronics Huizhou China Hohai University College of Computer and Information Nanjing China

ISBN: (纸本)9781728170862

With the development of information technology, mobile video on-demand and live streaming prevails in the young population. But the content of mobile video may contain some bloody and violent scenes. Teenagers, among all consumers, are more susceptible the negative influence of violence in videos. the censorship targeting at the online contents including images and video is an important yet arduous task. the adoption of AI-based censoring technique can help lower the operation cost for Internet content providers and save the work labor in censorship while preventing video consumers from being affected by unhealthy information. this paper presents an embedded system for content-based video censoring based on the deep learning technique. the proposed system is capable of filtering video content automatically, where an algorithm is developed that utilizes the power of Intel IoT development suite and the Intel Neural compute stick. Efforts has been made to optimize the real-time content censoring of the system. Experimental results show that, when applied to the video-on-demand IoT applications, the proposed system can speed up the video processing significantly and it can be effective in shielding young audience from violent videos at mobile devices in a real-time manner. © 2020 IEEE.

关键词： embedded systems

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2D Grid map for navigation based on LCSD-SLAM

2D Grid map for navigation based on LCSD-SLAM

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international conference on Information Science and Technology (ICIST)

作者： Yan Zhou Biye Li Dongli Wang Jinzhen Mu School of Autmomation and Electronic Information Xiangtan University Xiangtan China Shanghai Aerospace Control Technology Institute Shanghai China

this paper establishes a 2D grid map based on the semi-direct method, which can be used for navigation, sweeping robot and other applications. In order to implement the method with the help of the ROS platform, on the monocular semi-direct LCSD-SLAM method, after obtaining the key frames, a 2D grid map is constructed. Most of the current 3D to 2D map conversion research uses octrees for conversion, but we have proposed a threshold-based method, which is based on a monocular semi-direct method. After LCSD-SLAM obtains the key frame, through calculation, the 3D map is converted into a 2D grid map in real time. the A* path planning algorithm can be used to navigate in the 2D grid map. Experimental results show that the proposed method can successfully establish a 2D grid map and can be effectively applied in subsequent navigation.

关键词： Information science three-dimensional displays Navigation Octrees real-time systems Path planning Reliability

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Fault-Tolerant Regularity-Based real-time Virtual Resources 25

Fault-Tolerant Regularity-Based Real-Time Virtual Resources

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25th IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Cheng, Albert M. K. Dai, Guangli Paluri, Pavan Kumar Ansari, Mansoor Knape, Darrel Li, Yu Univ Houston Dept Comp Sci Houston TX 77004 USA Houston Mechatron Webster TX 77598 USA Virginia Tech Blacksburg VA 24060 USA

ISBN: (纸本)9781728131979

Many safety-critical applications employ embedded real-time systems where both timing and fault tolerance requirements must be continually satisfied. the Regularity-based Resource Partition Model (RRP), which is known for its code level independence between resource level and task level, is used to schedule resource partitions in virtualized real-time systems. this paper presents a fault tolerance model for Regularity-based real-time Virtual Resources to recover from transient hardware faults without modifying user applications. the proposed framework consists of a checkpointing mechanism called Fault-Tolerant RRP with a checkpointing partition followed by a redundancy partition prepared for re-execution to satisfy task deadlines despite the occurrence of faults. the frequency of checkpoints and the number of time slices in the redundancy partition are parameterized by the fault rate of the hardware resource and the sum of the availability factors of the original partition sets. Extensive theoretical analysis and simulation-based experiments show the effectiveness of the proposed framework while incurring minimal overhead.

关键词： Task analysis Fault tolerance Fault tolerant systems real-time systems Checkpointing Transient analysis Schedules

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Cellular Automata coupled with Memristor devices: A fine unconventional computing paradigm

Cellular Automata coupled with Memristor devices: A fine unc...

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19th international conference on Electronics, Information, and Communication (ICEIC)

作者： Ntinas, Vasileios Karamani, Rafailia-Eleni Fyrigos, Iosif-Angelos Vasileiadis, Nikolaos Stathis, Dimitrios Vourkas, Ioannis Dimitrakis, Panagiotis Karafyllidis, Ioannis Sirakoulis, Georgios Ch Democritus Univ Thrace Dept Elect & Comp Engn Xanthi Greece Univ Polytecn Catalunya Dept Elect Engn Barcelona Spain NCSR Demokritos Inst Microelect Athens Greece KTH Royal Inst Technol Dept Elect & Embedded Syst Stockholm Sweden Univ Tecn Federico Santa Maria Dept Elect Engn Valparaiso Chile

ISBN: (纸本)9781728162898

Cellular Automata (CAs), a ubiquitous computational tool proposed by John von Neumann, illustrate how great complexity emerges from simple rules of dynamical transitions between space and time interconnected simplistic entities. CAs perform as mathematical computation models, but also they are a powerful medium to model nature and natural systems. As a computational platform, CAs come with unified memory and computation in the same physical area, attributed as a strong candidate against the limitations of data transfer, known as the von Neumann bottleneck. On the other hand, Memristors with their inherent computing-In-Memory compatibility, can be easily considered as appropriate nanoelectronic devices to be coupled with CAs towards an energy and time efficient computational paradigm. In particular, CA present a vast area of applications, comprising various NP -complete hard to be solved problems arriving from computer science field, like the wellknown Shortest Path, Bin Packing, Knapsack and Max-clique problems, as well as physical, chemical and biological processes and phenomena, such as epileptic seizures in relation with healthy and pathogenic brain regions and, moreover, real life applications like pseudorandom number generation and simplistic, but with highly complex behavior, models like the famous Game of Life. the outcome of employing Memristors in CAs applications is promising in terms of parallelization, power consumption, scalability, reconfigurability, and high computing performance.

关键词： Cellular Automata Memristor Memristive System

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Electromigration and Power Analysis of Digital Circuits at 10 nm Technology Node before Signoff 11

Electromigration and Power Analysis of Digital Circuits at 1...

引用

11th international conference on computing, Communication and Networking Technologies, ICCCNT 2020

作者： Jat, Akanksha Panwalkar, Shweta Meena, Shweta School of VLSI Design and Embedded Systems National Institute of Technology Kurukshetra India Mixed Signal IP Group FAO Digital Design Team Intel Corporation Bangalore India National Institute of Technology Department of Electronics and Communication Engineering Kurukshetra India

ISBN: (纸本)9781728168517

With modern advancements in technology nodes and increasing design density, it is becoming more challenging to handle integrity and reliability checks as signoff verification steps. Electromigration (EM), IR drop, and power analysis play an important role as verification reliability signoff measures for any integrated circuits (ICs). As we step forward into advance technology nodes, the interconnect wire width becomes thinner along with transistor size. this makes the wire resistance more dominant at advance technology nodes like 10 nm and 7 nm. this increasing resistance introduces high IR drop and power issues which play significant role in the functionality failure of any electronic device with lower process technology nodes. Due to failures in hardware and functionality, more time and efforts are required for signoff. Electromigration analysis has also become a critical task due to technology scaling and increasing current density in small cross section area of routing wires. this work explores performance analysis in electromigration, voltage drop and power analysis using Redhawk tool. this work also discusses the factors affecting electromigration, voltage drop and power analysis and also the possible solutions to mitigate violations at signoff and in between physical designing stages. © 2020 IEEE.

关键词： Electromigration

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Lane Departure Warning System using TDA3x-rvp Board 11

Lane Departure Warning System using TDA3x-rvp Board

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11th international conference on computing, Communication and Networking Technologies, ICCCNT 2020

作者： Bhargav, Suhas N Prasad, V Akshatha RV College of Engineering Dept. ECE Bengaluru India Amrita School of Engineering Dept. EEE Coimbatore India

ISBN: (纸本)9781728168517

the man's desire to own luxury cars has always shown an increasing growth. From past 10 years, the number of vehicles that are sold in India have skyrocketed. this trend has a direct impact on the number of accidents that are occurring on Indian roads. Nearly, 1.35 million road traffic fatalities occur annually. In majority of the cases, accident occurs when one car comes into the path of the other which is caused due to the risk of driver losing his control over the car. this raises the need for advanced technologies to alert drivers of potential hazards and allow drivers to take good time taking control of the vehicle. One of the Advanced Driver Assistance systems (ADAS), lane departure warning system (LDWS) helps drivers to avoid these tragedies. In this paper, the above mentioned system is developed using TDA3x-RVP board as this is a highly optimized and robust set of tools designed to meet automotive industry requirements. It is also conveniently flexible in the existing framework and can be expanded to incorporate other applications. the proposed approach detects the lanes by determining the number of left lane points and the right lane points based on certain rho and theta threshold parameters, and warns the driver in case of unintentional lane shifts that can be either left lane or right lane. © 2020 IEEE.

关键词： Advanced driver assistance systems

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Partitioned Scheduling for Dependency Graphs in Multiprocessor real-time systems 25

Partitioned Scheduling for Dependency Graphs in Multiprocess...

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25th IEEE international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Shi, Junjie Ueter, Niklas von der Brueggen, Georg Chen, Jian-Jia TU Dortmund Univ Dortmund Germany

ISBN: (纸本)9781728131979

Effectively handling precedence constraints and resource synchronization is a challenging problem in the era of multiprocessor systems even with massively parallel computation power. One common approach is to apply list scheduling to a given task graph with precedence constraints. However, in some application scenarios, such as the OpenMP task model and multiprocessor partitioned scheduling for resource synchronization using binary semaphores, several operations can be forced to be tied to the same processor, which invalidates the list scheduling. this paper studies a special case of this challenging scheduling problem, where a task comprised of (at most) three subtasks is executed sequentially on the same processor and the second subtasks of the tasks may have sequential dependencies, e.g., due to synchronization. We demonstrate the limits of existing algorithms and provide effective heuristics considering preemptive execution. the evaluation results show a significant improvement, compared to the existing multiprocessor partitioned scheduling strategies.

关键词： Task analysis Processor scheduling real-time systems Synchronization Partitioning algorithms Schedules Protocols

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An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor embedded systems 2020

An OpenMP Parallel Genetic Algorithm for Design Space Explor...

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11th Workshop on Parallel Programming and Run-time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore embedded computing Platforms, PARMA-DITAM 2020

作者： Muttillo, Vittoriano Giammatteo, Paolo Fiorilli, Giuseppe Pomante, Luigi University of L’Aquila L’Aquila Italy

ISBN: (纸本)9781450375450

Heterogeneous multiprocessor platforms are becoming widespread in the embedded system domain, mainly for the opportunity to improve timing performance and to minimize energy/power consumption and costs. therefore, when using such platforms, it is important to adopt a Design Space Exploration (DSE) strategy that considers compromises among different objectives. Existing DSE approaches are generally based on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOPs) by minimizing a linear combination of weighted cost functions (i.e., Weighted Sum Method, WSM). In this way, the main issues are related to reduce timing execution while trying to improve the evolutionary algorithm performance, introducing strategies that attempt to bring better solutions. Code parallelization is one of the most used approaches in this field, but no standard methods have been released since different aspects could affect the performance. this approach leads to exploit parallel and distributed processing elements in order to implement evolutionary algorithms. In the latter case, if we consider genetic algorithms, it is possible to talk about Parallel Genetic Algorithms (PGA). Considering this context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an improvement that reduces execution time using parallel programming languages (i.e., OpenMP) inside the main genetic algorithm approach, while trying to lead to better partitioning solutions. the descriptions of the adopted DSE activities and the OpenMP implementation, validated by means of a case study, represent the core of the paper. © 2020 Association for computing Machinery.

关键词： Multiobjective optimization

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