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Optimizations of a Linear Matrix Solver in a Composite Simulation for a Vector Computer

Optimizations of a Linear Matrix Solver in a Composite Simul...

引用

International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Zhilin He Kazuhiko Komatsu Masayuki Sato Hiroaki Kobayashi Graduate School of Information Sciences Tohoku University Sendai Japan Cyberscience Center Tohoku University Sendai Japan

ISBN: (纸本)9781665496407

A fiber-reinforced composite simulation based on a spring-element model can capture the stress field of composites. Since the simulation can calculate the maximum stress to composites, it is essential to discover a more reliable composite structure, and the acceleration of the simulation is required. However, a linear matrix solver in the simulation needs a long execution time and a vast memory bandwidth to solve element displacements of the structure, especially for large-scale composites. To accelerate the simulation, this paper proposes a vectorization method of a linear matrix solver on a vector computer. By applying loop optimizations such as splitting, unrolling, distribution, and interchange, efficient vector computing is realized. From the performance evaluation, it is shown that the optimizations achieve more than 15.5× speedups on the vector computer. Furthermore, the optimized simulation on a vector computer achieves a 2.4× to 3.7× speedup compared with the original version on the Intel Xeon.

关键词： Performance evaluation Computational modeling Bandwidth Programming parallel architectures Reliability Optimization

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A parallel Algorithm to Construct Node-Independent Spanning Trees on the Line Graph of Locally Twisted Cube

A Parallel Algorithm to Construct Node-Independent Spanning ...

引用

International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Zhiyong Pan Baolei Cheng Jianxi Fan Huanwen Zhang School of Computer Science and Technology Soochow University Suzhou China

ISBN: (纸本)9781665496407

An interconnection network can be abstracted into a graph, and the basic mathematical research in the graph can provide a good reference for the research in the practical application. the study of node-independent spanning trees (node-ISTs) in a graph has received extensive attention because of their application in reliable communication, fault-tolerant broadcasting and secure message distribution, and has achieved remarkable results on many special networks. But there are few results in the line graph of them. As one of the typical variations of hypercube, locally twisted cube has many excellent properties, whose line graph has all the advantages of locally twisted cube. So it makes sense to do some research on the line graph of locally twisted cube. In this paper, we propose a parallel algorithm to construct $2n-2$ node-ISTs rooted at node $[u,\ N(u, 2)]$ , where $u$ is an arbitrary node on locally twisted cube and $n\geq 1$ . And the correctness of our algorithm is proved.

关键词： Fault tolerance Fault tolerant systems Programming NIST Broadcasting Hypercubes parallel architectures

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Accelerating a Lossy Compression Method with Fine-Grained parallelism on a GPU

Accelerating a Lossy Compression Method with Fine-Grained Pa...

引用

International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Yifan Wu Jingcheng Shen Masao Okita Fumihiko Ino Graduate School of Information Science and Technology Osaka University Osaka Japan

ISBN: (纸本)9781665496407

With the rapid increase of data size processed by nowadays applications, high-performance compression methods become important to reduce both the memory consumption and the amount of data transfer. However, unlike the studies on CPU-based compression methods, those on GPU-based compression methods are insufficient. In this work, we target a lossy compression method that reported a high performance on a CPU-centric supercomputer. We propose schemes with fine-grained parallelism to accelerate the CPU-based method on the GPU, solving data dependency and write conflict issues in compression and decompression processes. Experimental results show that the proposed method achieved both higher performance, i.e., 42.0x and 1.9x speedups at best compared to the original method and a state-of-the-art GPU-based lossy compression method, respectively. Moreover, the proposed method achieved at best 1.2x and 1.8x as large as the compression ratio achieved by the original method and the state-of-the-art GPU-based lossy compression method, respectively.

关键词： Memory management Graphics processing units parallel processing Programming Data transfer Supercomputers parallel architectures

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Joint Optimization of Path Planning and Task Assignment for Space Robot

Joint Optimization of Path Planning and Task Assignment for ...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Yifei Sun Zikai Zhang Yidong Li Jigang Wu School of Computer Science and Technology Guangdong University of Technology Guangzhou China School of Computer and Information Technology Beijing Jiaotong University State Key Lab of Rail Traffic Control and Safety Beijing Jiaotong University

ISBN: (纸本)9781665496407

the space robot has been used widely in the aerospace industry. Because of the special working environment and limited fuel, an appropriate path is necessary for space robots to work. this paper investigates the path planning for multiple space robots to execute exploration tasks. To reduce the completion latency of exploration tasks, we model the joint problem of path planning and task assignment. then we propose a combination algorithm named Branch addition path planning and Task Assignment (BTA). Finally, we implement a series of experiments to evaluate the performance of the proposed algorithms. Experimental results show that the proposed algorithm performs better than the Random path planning and Task Assignment algorithm (RTA) constructed also in this paper. Specifically, BTA performs better than RTA in terms of completion latency and BTA can save more fuel than RTA. Furthermore, the path planning algorithms forward search branch addition of BTA performs more stably than the random path planning of RTA in terms of running time.

关键词： Service robots Programming Path planning Space exploration parallel architectures Fuels Task analysis

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Vertex-Disjoint Paths in BCDC Networks

Vertex-Disjoint Paths in BCDC Networks

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Xi Wang Jianxi Fan Suzhou Institute of Industrial Technology Suzhou China Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education Jilin University Changchun P.R. China School of Computer Science and Technology Soochow University Suzhou China

ISBN: (纸本)9781665496407

For any integer $n\geq 2,\ B_{n}$ , the $n$ -dimensional BCDC network, based on a class of BC networks, crossed cube, is a server-centric and high-performance data center network for mega data centers with manageable cabling complexity. Implementing vertex-disjoint paths has great value of application in fault-tolerance and multi-path routing of data center networks. In this paper, we construct $n$ vertex-disjoint paths joining every two distinct vertices in $B_{n}$ , whose maximum length is limited by $\lceil\frac{n}{2}\rceil+5$ , where the diameter of $B_{n}$ is $\lceil\frac{n+1}{2}\rceil+1$ . Our results are fundamental and essential for fault-tolerance and multi-path routing in BCDC networks.

关键词： Data centers Fault tolerance Fault tolerant systems Programming Routing parallel architectures Complexity theory

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Efficient 1D Barcode Localization Method for Imagery Shipping Label Using Deep Learning Models

Efficient 1D Barcode Localization Method for Imagery Shippin...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Lang-chao Qiao Jin-lu Wang Bao-hong Gao Xin-gang Yang Wen-tao Feng Yu-xiao Zhang Yan Wang Hai Liu Wei Liu Division of Monopoly Administratin Shaanxi Branch China National Tobacco Corporation Xi'an China Gaoxin District Branch Xi'an Tobacco Monopoly Administration Xi'an China School of Computer Science and Technology Xi'an University of Posts and Telecommunications Xi'an China

ISBN: (纸本)9781665496407

In this paper, an efficient approach for imagery shipping label 1D barcode localization integrated with two deep learning models is proposed. In the first stage, a Faster R-CNN model is adopted to detect the barcode region existed in the imagery shipping label automatically. then orientation of parallel lines of 1D barcode can be computed by using Line Segment Detector algorithm. Next, the tilt angle of the image will be corrected using the direction information for rotation correction. Finally, in order to decode barcode accurately in the subsequent stage after barcode localization, a Resnet-34 model was used as a multi-class classifier to determinate the orientation of the shipping label and calibrate the whole image. Using a dataset that contains a total of 1830 imagery shipping labels including slanted ones or ones with complex background, our method can yield a barcode localization accuracy of 0.9866, which demonstrates its encouraging performance.

关键词： Location awareness Deep learning Image segmentation Computational modeling Detectors Programming parallel architectures

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A Heuristic SAT Problems Solving Method based on LSTM Network

A Heuristic SAT Problems Solving Method based on LSTM Networ...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Yichuan Wang Xiaolong Liang Xinhong Hei Lei Zhu Wenjiang Ji College of Computer Science and Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781665496407

Boolean Satisfiability Problem(SAT) is a well known determination Problem. *** proved in 1971 that SAT Problem is the first NP-Complete (NPC) Problem in the world, namely, any non-deterministic Polynomial (NP) Problem can be specified with the SAT Problem for solving in Polynomial time. therefore, Boolean satisfiability problem (SAT) can be extended to many practical applications, such as integrated circuit design optimization, biological genes, artificial intelligence, Internet, etc. And there are a lot of NP problems in cryptography. therefore, the study of SAT Problem is of great significance to cryptography. In this paper, we design a heuristic SAT solving algorithm based on LSTM (Long Short-Term Memory) recurrent neural networks. First of all, based on LSTM, we train the model as an end-to-end SAT Solver, which can output 0 or 1 to represent the satisfiability of each SAT problem. then we extract the high-dimensional output of the LSTM network and carry out k-means clustering analysis. Finally, we assign the obtained results as the initial value of the variables of the SAT problem, and inspire two types of classical algorithms (complete algorithm and incomplete algorithm) to solve the SAT problem respectively, so as to accelerate the solving process. In the experiment, we demonstrated the test results of SAT problems with different sizes, and the results show that the LSTM-WalkSAT and LSTM-DPLL based heuristic SAT solving methods can significantly improve the solving efficiency of the original complete or incomplete SAT solving algorithms.

关键词： Integrated circuit synthesis Recurrent neural networks Heuristic algorithms Clustering algorithms Programming parallel architectures Internet

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Reducing TLB Miss Penalty on GPUs via Unified Multi-level PWB and PWC

Reducing TLB Miss Penalty on GPUs via Unified Multi-level PW...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Yang Lin Dunbo Zhang Chaoyang Jia Qiong Wang Li Shen School of Computer NUDT Changsha China

ISBN: (纸本)9781665496407

Recently, GPUs are found to be used across a broad range of domains. To support virtual memory, which is required by most applications at present, the address translation process is introduced to GPU side. However, many applications demonstrate that an irregular memory access pattern, in which accesses are poor structured and often data dependent, makes performance worse especially with virtual-to-physical address translations. Modern memory management unit (MMU) employs caching, e.g. page walk buffer (PWB) and page walk cache (PWC), and scheduling mechanisms to accelerate address translations after TLB misses. Constrained by the linear table structure of traditional PWB and PWC, they hold lots of redundant information, which further limits the performance of irregular applications. Although nonlinear structure can eliminate the redundancy, it requires sequential look-up on PWB and PWC, which brings greater performance loss. In this paper, we propose a unified multi-level PWB and PWC structure that can eliminate the redundancy while enabling parallel look-up. We also design four corresponding address translation processes to ensure the efficiency of the new structure. We evaluate our design with real-world benchmarks under GPGPU-Sim simulator. Results show that our design achieves 42.6% IPC improvement.

关键词： Memory management Graphics processing units Termination of employment Programming Benchmark testing parallel architectures

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Mapping YOLOv4-Tiny on FPGA-Based DNN Accelerator by Using Dynamic Fixed-Point Method

Mapping YOLOv4-Tiny on FPGA-Based DNN Accelerator by Using D...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Peng Li Cheng Che State Key Laboratory of Information Security Institute of Information Engineering Chinese Academy of Sciences Beijing China School of Cyber Security University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665496407

In the past few decades, with the large-scale application of deep learning technology, the neural network inference speed problem is becoming more and more severe, especially in some mobile and embedded real-time processing systems. To improve the inference speed, some software optimization techniques have been proposed by previous researchers. However, these methods only focused on the model self and still cannot meet the rapid development of large and complex deep learning models. Fortunately, deep neural network (DNN) accelerators based on FPGA SoC has opened a promising opportunity for the real-time inference. In this paper, we proposed a novel 16-bit dynamic fixed-point number quantization method to map the object detection network YOLOv4-tiny into FPGA-based heterogeneous deep learning accelerators. We evaluate this model in Xilinx Zynq-7020 SoC on the ZedBoard platform. Experiment on coco dataset shows that this approach can improve the model inference speed to 4× than pure CPU platform, and the accuracy loss is negligible with only 3-5%. this mapping method can be competitive with or even superior to other state-of-the-art accelerating method in deep learning fields.

关键词： Deep learning Quantization (signal) Neural networks Programming Real-time systems Software parallel architectures

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FEAS: A Faster Event-driven Accelerator Supporting Inhibitory Spiking Neural Network

FEAS: A Faster Event-driven Accelerator Supporting Inhibitor...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Songsong Li Lei Gong Teng Wang Chao Wang Xuehai Zhou University of Science and Technology of China Heifei China

ISBN: (纸本)9781665496407

In recent years, the spiking neural network (SNN) has gained widespread attention for its low latency and low power consumption characteristics. Customizing accelerators to exploit the parallelism in SNN fully has become a current research hotspot. Because the calculations between different time steps in SNN have dependencies, the existing accelerators update the neuron state strictly in time sequence, which results in the calculation of SNN even more than that of the artificial neural network (ANN). In addition, traditional event-driven SNN accelerators cannot support inhibitory SNN models, which severely limits their scope of application. Based on this observation, we combined the characteristics of the most commonly used neuron model and spike code to design an event-driven SNN accelerator (FEAS). FEAS realizes the acceleration for SNN (both the excitatory SNN and the inhibitory SNN) models through algorithm approximation and novel hardware modules. We use FEAS to accelerate a fully connected SNN model for classification on the MNIST dataset. the results show that compared with the state-of-the-art technology, our accelerator can increase the throughput by an order of magnitude with the model's accuracy as high as 97.54%.

关键词： Power demand Neurons Artificial neural networks Programming parallel processing Approximation algorithms throughput

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