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共 122 条记录，以下是21-30 订阅

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Multi-model Stacking Ensemble Learning for Student Achievement Prediction

Multi-model Stacking Ensemble Learning for Student Achieveme...

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International symposium on parallel architectures, algorithms and Programming (PAAP)

作者： Tao Fang Sirui Huang Ya Zhou Huibing Zhang Guangxi Key Laboratory of Trusted Software Guilin University of Electronic Technology Guilin China

ISBN: (纸本)9781665496407

Educational data mining has always been a direction of big data applications, among which the student achievement prediction is one of the research focuses. the research has two main objects, one is online education, and the other is school education. Due to the prevalence of online education and the relatively easy collection of data, many studies have focused on the prediction of student achievement in online education. At the same time, the differences in teaching methods, student habits, and technical development levels of schools in different regions have led to a slight deviation in the main research areas and research emphasis on student achievement prediction. In China, due to the difficulties of traditional schools in collecting student academic data, relevant research can only use limited grade data and campus card data. this method has limitations that are not easy to promote. this paper uses a more easily collected score data, combined with multi-model stacking ensemble learning (MMSE) model to predict students' achievement. the model mainly includes two parts: data preprocessing and model construction. In the data preprocessing part, the data features are designed using the students' grades and course information. In the model building part, a two-layer integrated learning model is established. In the first layer, 5-fold cross-validation is used to train 5 different basic classifiers. the second layer uses the regression algorithm combined with the prediction results of the first layer to predict student achievement. the results show that using the data combined with appropriate feature engineering to make predictions can get very satisfactory results.

关键词： Education Stacking Data preprocessing Predictive models Prediction algorithms Data models parallel architectures

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DAPPER: Data Aware Approximate NoC for GPGPU architectures 12

DAPPER: Data Aware Approximate NoC for GPGPU Architectures

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12th IEEE/acm International symposium on Networks-on-Chip (NOCS)

作者： Raparti, Venkata Yaswanth Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

ISBN: (纸本)9781538648933

High interconnect bandwidth is crucial to achieve better performance in many-core GPGPU architectures that execute highly data parallel applications. the parallel warps of threads running on shader cores generate a high volume of read requests to the main memory due to the limited availability of data cache space at the shader cores. this leads to scenarios with rapid arrival of reply data from the DRAM, which creates a bottleneck at memory controllers (MCs) that send reply packets back to the requesting cores over the NoC. Coping with such high volumes of data requires NoC architectures that possess high power overhead. To accomplish high bandwidth and low energy communication in GPGPUs, we propose Dapper, a data-aware approximate NoC architecture that increases the utilization of the available bandwidth by using low power single cycle overlay circuits for the reply traffic between MCs and shader cores. Dapper also incorporates a novel MC architecture that leverages the inherent approximability of the data values of certain applications and reduces the number of reply packets injected into the NoC by the MCs. Experimental results show that Dapper reduces the energy consumed in the GPGPU by up to 50% with up to 99% application output accuracy and minimum performance overheads compared to a state-of-the-art approximate NoC architectures.

关键词： GPGPU approximate computing network-on-chip

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ParaRegex: Towards Fast Regular Expression Matching in parallel 16

ParaRegex: Towards Fast Regular Expression Matching in Paral...

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12th acm/IEEE symposium on architectures for Networking and Communications Systems (ANCS)

作者： Fu, Zhe Liu, Zhi Li, Jun Tsinghua Univ Dept Automat Beijing Peoples R China Tsinghua Univ Res Inst Informat Technol Beijing Peoples R China Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781450341837

In this paper, we propose ParaRegex, a novel approach for fast parallel regular expression matching. ParaRegex is a framework that implements data-parallel regular expression matching for deterministic finite automaton based methods. Experimental evaluation shows that ParaRegex produces a fast matching engine with speeds of up to 6 times compared to sequential implementations on a commodity 8-thread workstation.

关键词： Deep inspection Regular expression matching DFA parallelism

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PANDA: Extreme Scale parallel K-Nearest Neighbor on Distributed architectures 30

PANDA: Extreme Scale Parallel K-Nearest Neighbor on Distribu...

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30th IEEE International parallel and Distributed Processing symposium (IPDPS)

作者： Patwary, Md. Mostofa Ali Satish, Nadathur Rajagopalan Sundaram, Narayanan Liu, Jialin Sadowski, Peter Racah, Evan Byna, Suren Tull, Craig Bhimji, Wahid Prabhat Dubey, Pradeep Intel Corp Santa Clara CA 95051 USA Lawrence Berkeley Natl Lab Berkeley CA USA Univ Calif Irvine Irvine CA 92717 USA

ISBN: (纸本)9781509021406

Computing k-Nearest Neighbors (KNN) is one of the core kernels used in many machine learning, data mining and scientific computing applications. Although kd-tree based O(log n) algorithms have been proposed for computing KNN, due to its inherent sequentiality, linear algorithms are being used in practice. this limits the applicability of such methods to millions of data points, with limited scalability for Big Data analytics challenges in the scientific domain. In this paper, we present parallel and highly optimized kd-tree based KNN algorithms (both construction and querying) suitable for distributed architectures. Our algorithm includes novel approaches for pruning search space and improving load balancing and partitioning among nodes and threads. Using TB-sized datasets from three science applications: astrophysics, plasma physics, and particle physics, we show that our implementation can construct kd-tree of 189 billion particles in 48 seconds on utilizing similar to 50,000 cores. We also demonstrate computation of KNN of 19 billion queries in 12 seconds. We demonstrate almost linear speedup both for shared and distributed memory computers. Our algorithms outperforms earlier implementations by more than order of magnitude;thereby radically improving the applicability of our implementation to state-of-the-art Big Data analytics problems.

关键词： Big Data Analytics KNN kd-tree Classification parallel algorithms and Load Balancing

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parallel approaches to the string matching problem on the GPU 16

Parallel approaches to the string matching problem on the GP...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Ashkiani, Saman Amenta, Nina Owens, John D. University of California Davis United States

ISBN: (纸本)9781450342100

We design a family of parallel algorithms and GPU implementations for the exact string matching problem, based on Rabin-Karp (RK) randomized string matching. We describe and analyze three primary parallel approaches to binary string matching: cooperative (CRK), divide-and-conquer (DRK), and a novel hybrid of both (HRK). the CRK is most effective for large patterns (>8K characters), while the DRK approach is superior for shorter patterns. We then generalize the DRK to support any alphabet size without loss of performance. Our DRK method achieves up to a 64 GB/s processing rate on 8-character patterns from an 8-bit alphabet on an NVIDIA Tesla K40c GPU. We next demonstrate a novel parallel two-stage matching method (DRK-2S), which first skims the text for a smaller subset of the pattern and then verifies all potential matches in parallel. Our DRK-2S method is superior for pattern sizes up to 64k compared to the fastest CPU-based string matching implementations. With an 8-bit alphabet and up to 1k-character patterns, we get a geometric mean speedup of 4.81x against the best CPU methods, and can achieve a processing rate of at least 53 GB/s.

关键词： Graphics processing unit

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Extending the nested parallel model to the nested dataflow model with provably efficient schedulers 16

Extending the nested parallel model to the nested dataflow m...

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28th acm symposium on parallelism in algorithms and architectures, SPAA 2016

作者： Dinh, David Simhadri, Harsha Vardhan Tang, Yuan Computer Science Division Univ. of California Berkeley BerkeleyCA94720 United States Computer Science Dept. Lawrence Berkeley National Lab. BerkeleyCA94720 United States School of Software Fudan Univ. Shanghai Key Lab. of Intelligent Information Processing Shanghai200433 China

ISBN: (纸本)9781450342100

the nested parallel (a.k.a. fork-join) model is widely used for writing parallel programs. However, the two composition constructs, i.e. "k" (parallel) and "k" (serial), that comprise the nested-parallel model are insufficient in expressing "partial dependencies" in a program. We propose a new dataflow composition construct "" to express partial dependencies in algorithms in a processorand cache-oblivious way, thus extending the Nested parallel (NP) model to the Nested Dataflow (ND) model. We redesign several divide-and-conquer algorithms ranging from dense linear algebra to dynamic-programming in the ND model and prove that they all have optimal span while retaining optimal cache complexity. We propose the design of runtime schedulers that map ND programs to multicore processors with multiple levels of possibly shared caches (i.e, parallel Memory Hierarchies) and prove guarantees on their ability to balance nodes across processors and preserve locality. For this, we adapt space-bounded (SB) schedulers for the ND model. We show that our algorithms have increased "parallelizability" in the ND model, and that SB schedulers can use the extra parallelizability to achieve asymptotically optimal bounds on cache misses and running time on a greater number of processors than in the NP model. the running time for the algorithms in this paper is(Equation presented on a p-processor machine, where Q∗ is the parallel cache complexity of task t, Ci is the cost of cache miss at level-i cache which is of size Mi, and σ ∈ (0,1) is a constant.

关键词： parallel processing systems

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parallel Implementation Strategies for Hierarchical Non-Uniform Memory Access Systems by Example of the Scale-Invariant Feature Transform Algorithm 30

Parallel Implementation Strategies for Hierarchical Non-Unif...

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30th IEEE International parallel and Distributed Processing symposium (IPDPS)

作者： Plauth, Max Hagen, Wieland Feinbube, Frank Eberhardt, Felix Feinbube, Lena Polze, Andreas Univ Potsdam Hasso Plattner Inst Software Syst Engn Operating Syst & Middleware Grp Potsdam Germany

ISBN: (纸本)9781509036820

the domains of parallel and distributed computing have been converging continuously up to the degree that state-of-the-art server computer systems incorporate characteristics from both domains: they comprise a hierarchy of enclosures, where each enclosure houses multiple processor sockets and each socket again contains multiple memory controllers. A global address space and cache coherency are facilitated using multiple layers of fast interconnection technologies even across enclosures. the growing popularity of such systems creates an urge for efficient mappings of cardinal algorithms onto such hierarchical architectures. However, the growing complexity of such systems and the inconsistencies between implementation strategies of different hardware vendors make it increasingly harder to do find efficient mapping strategies that are universally valid. In this paper, we present scalable optimization and mapping strategies in a case study of the popular Scale-Invariant Feature Transform (SIFT) computer vision algorithm. Our approaches are evaluated using a state-of-the-art hierarchical Non-Uniform Memory Access (NUMA) system with 240 physical cores and 12 terabytes of memory, apportioned across 16 NUMA nodes (sockets). SIFT is particularly interesting since the algorithm utilizes a variety of common data access patterns, thus allowing us to discuss the scaling properties of optimization strategies from the distributed and parallel computing domains and their applicability on emerging server systems.

关键词： parallel programming Memory management Multiprocessor interconnection networks Network topology

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Space and Time Efficient parallel Graph Decomposition, Clustering, and Diameter Approximation 15

Space and Time Efficient Parallel Graph Decomposition, Clust...

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27th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Ceccarello, Matteo Pietracaprina, Andrea Pucci, Geppino Upfal, Eli Univ Padua Dept Informat Engn Padua Italy Brown Univ Dept Comp Sci Providence RI 02912 USA

ISBN: (纸本)9781450335881

We develop a novel parallel decomposition strategy for un-weighted, undirected graphs, based on growing disjoint connected clusters from batches of centers progressively selected from yet uncovered nodes. With respect to similar previous decompositions, our strategy exercises a tighter control on both the number of clusters and their maximum radius. We present two important applications of our parallel graph decomposition: (1) k-center clustering approximation;and (2) diameter approximation. In both cases, we obtain algorithms which feature a polylogarithmic approximation factor and are amenable to a distributed implementation that is geared for massive (long-diameter) graphs. the total space needed for the computation is linear in the problem size, and the parallel depth is substantially sublinear in the diameter for graphs with low doubling dimension. To the best of our knowledge, ours are the first parallel approximations for these problems which achieve sub-diameter parallel time, for a relevant class of graphs, using only linear space. Besides the theoretical guarantees, our algorithms allow for a very simple implementation on clustered architectures: we report on extensive experiments which demonstrate their effectiveness and efficiency on large graphs as compared to alternative known approaches.

关键词： parallel Graph algorithms Graph Decomposition k-Center Problem Diameter Approximation MapReduce

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Optimal Performance Prediction of ADAS algorithms on Embedded parallel architectures 17

Optimal Performance Prediction of ADAS Algorithms on Embedde...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Saussard, Romain Bouzid, Boubker Vasiliu, Marius Reynaud, Roger Renault SAS Guyancourt France Univ Paris 11 Inst Elect Fondamentale Orsay France

ISBN: (纸本)9781479989379

ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit. Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial. In fact it is not a simple task for automotive industry actors to choose the most suited heterogeneous SoC for a given application. Moreover, embedding complex algorithms on these systems remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on the different computing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processing algorithms applicable on different types of computing units. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms, and a few characteristics of computing units.

关键词： Heterogeneous architectures Embedded Systems Performance Prediction Image Processing

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CUDA Grid-Level Task Progression algorithms 17

CUDA Grid-Level Task Progression Algorithms

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Kartsaklis, Christos Joubert, Wayne Hernandez, Oscar R. Eisenbach, Markus Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781479989379

Tasking is a prominent parallel programming model. In this paper we conduct a first study into the feasibility of task-parallel execution at the CUDA grid, rather than the stream/kernel level, for regular, fixed in-out dependency task graphs, similar to those found in wavefront computational patterns, making the findings broadly applicable. We propose and evaluate three CUDA task progression algorithms, where threadblocks cooperatively process the task graph, and argue about their performance in terms of tasking throughput, atomics and memory IO overheads. Our initial results demonstrate a throughput of 38 million tasks/second on a Kepler K20X architecture.

关键词： parallel architectures parallel programming CUDA grid-level task progression algorithm CUDA task progression algorithm Kepler K20X architecture parallel programming model wavefront computational pattern Computational modeling Graphics processing units Instruction sets Kernel parallel processing Radiation detectors Runtime

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