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检索条件"任意字段=12th ACM Symposium on Parallel Algorithms and Architectures"

共 122 条记录，以下是31-40 订阅

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Evaluation of Hybrid parallel Cell List algorithms For Monte Carlo Simulation 17

Evaluation of Hybrid Parallel Cell List Algorithms For Monte...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Rushaidat, Kamel Schwiebert, Loren Jackman, Brock Mick, Jason Potoff, Jeffrey Wayne State Univ Dept Comp Sci Detroit MI 48202 USA Wayne State Univ Dept Chem Engn & Mat Sci Detroit MI USA

ISBN: (纸本)9781479989379

this paper describes efficient, scalable parallel implementations of the conventional cell list method and a modified cell list method to calculate the total system intermolecular Lennard-Jones force interactions in the Monte Carlo Gibbs ensemble. We targeted this part of the Gibbs ensemble for optimization because it is the most computationally demanding part of the force interactions in the simulation, as it involves all the molecules in the system. the modified cell list implementation reduces the number of particles that are outside the interaction range by making the cells smaller, thus reducing the number of unnecessary distance evaluations. Evaluation of the two cell list methods is done using a hybrid MPI+OpenMP approach and a hybrid MPI+CUDA approach. the cell list methods are evaluated on a small cluster of multicore CPUs, Intel Phi coprocessors, and GPUs. the performance results are evaluated using different combinations of MPI processes, threads, and problem sizes.

关键词： Cell List Monte Carlo Simulations Hybrid parallel architectures Gibbs Ensemble

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A Data-oriented Method for Scheduling Dependent Tasks on High-density Multi-GPU Systems 17

A Data-oriented Method for Scheduling Dependent Tasks on Hig...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Zhang, Peng Gao, Yuxiang Qiu, Meikang SUNY Stony Brook Dept Biomed Engn Stony Brook NY 11794 USA Cray Inc Cluster Solut Dept San Jose CA USA Pace Univ Dept Comp Sci New York NY 10038 USA

ISBN: (纸本)9781479989379

the rapidly-changing computer architectures, though improving the performance of computers, have been challenging the programming environments for efficiently harnessing the potential of novel architectures. In this area, though the high-density multi-GPU architecture enabled unparalleled performance advantage of dense GPUs in a single server, it has increased the difficulty for scheduling diversified and dependent tasks. We therefore propose a data-oriented method for scheduling dependent tasks for this architecture while providing its implementation. In our method, we model a parallel program as a collection of data-dependent tasks for which data dependencies are managed by an expressive matrix. Accordingly, we develop a hierarchical scheduler infrastructure for our model. In this, a top scheduler is built for querying the data-dependency matrix;three downstream schedulers for queuing computation tasks that are exclusively assigned to processor, accelerator or either;and a multitude of bottom schedulers each for providing a processing element with assigned tasks. We experiment our scheduler for examples of Strassen matrix multiplication and Cholesky matrix inversion algorithms on a computer that has 8 Tesla K40 GPUs. the results show that our method is capable of offering the efficient task parallelism while fulfilling the complex task dependencies. When advanced task-oriented schedulers have been widely designed for distributed systems, a lightweight data-driven scheduler could be an alternative and handy approach that can handle the dependent yet diversified tasks of data-intensive applications for the novel high-density multi-accelerator system.

关键词： data scheduling task scheduling parallel computing heterogeneous multi-GPU systems

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Autotuning GPU-accelerated QAP Solvers for Power and Performance 17

Autotuning GPU-accelerated QAP Solvers for Power and Perform...

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2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC)

作者： Chaparala, Abhilash Novoa, Clara Qasem, Apan Texas State Univ Dept Comp Sci San Marcos TX 78666 USA Texas State Univ Ingram Sch Engn San Marcos TX USA

ISBN: (纸本)9781479989379

the Quadratic Assignment Problem (QAP) is an important combinatorial optimization problem with applications in many areas including operations research and chip design. QAP is known to be NP-hard and requires heuristic approaches for most real data sets. Although many algorithms have been proposed for solving QAPs, few have attempted to exploit the fine-grain data parallelism available on accelerator architectures and none have considered aspects of energy efficiency. In this paper, we present GPU-accelerated implementations of two QAP algorithms. We parameterize each algorithmic variant along several dimensions including thread granularity, occupancy, shared memory usage and register pressure. We develop an autotuning framework that explores this space of execution parameters and yields CUDA binaries that are efficient in terms of both performance and power consumption. We demonstrate the effectiveness of our tuning framework on an Nvidia Tesla K20c. On a series of experiments on the well-known QAPLIB data sets, our autotuned solutions run at least an order-of-magnitude faster than baseline implementations. the experimental results also provide key insight into the performance characteristics of accelerated QAP solvers. In particular, the results reveal that both algorithmic choice and the shape of the input data sets are key factors in finding an efficient implementation.

关键词： autotuning energy efficiency parallel performance

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Optimal Performance Prediction of ADAS algorithms on Embedded parallel architectures

Optimal Performance Prediction of ADAS Algorithms on Embedde...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Romain Saussard Boubker Bouzid Marius Vasiliu Roger Reynaud Renault S.A.S Guyancourt France Instutut d'Electronique Fondamentale Université Paris Sud Orsay France

ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit. Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial. In fact it is not a simple task for automotive industry actors to choose the most suited heterogeneous SoC for a given application. Moreover, embedding complex algorithms on these systems remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on the different computing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processing algorithms applicable on different types of computing units. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms, and a few characteristics of computing units.

关键词： Kernel Computer architecture Image processing Graphics processing units Prediction algorithms parallel processing Computational modeling

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Evaluation of Hybrid parallel Cell List algorithms For Monte Carlo Simulation

Evaluation of Hybrid Parallel Cell List Algorithms For Monte...

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IEEE International symposium on Cyberspace Safety and Security

作者： Kamel Rushaidat Loren Schwiebert Brock Jackman Jason Mick Jeffrey Potoff Department of Computer Science Wayne State University Department of Chemical Engineering and Materials Science Wayne State University

ISBN: (纸本)9781479989386

关键词： Cell List Monte Carlo Simulations Hybrid parallel architectures Gibbs Ensemble

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parallel Streaming Frequency-Based Aggregates 14

Parallel Streaming Frequency-Based Aggregates

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26th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Tangwongsan, Kanat Tirthapura, Srikanta Wu, Kun-Lung Mahidol Univ Int Coll Comp Sci Program Bangkok Thailand Iowa State Univ Dept Elect & Comp Engn Ames IA USA IBM TJ Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9781450328210

We present efficient parallel streaming algorithms for fundamental frequency-based aggregates in both the sliding window and the infinite window settings. In the sliding window setting, we give a parallel algorithm for maintaining a space-bounded block counterd (SBBC). Using SBBC, we derive algorithms for basic counting, frequency estimation, and heavy hitters that perform no more work than their best sequential counterparts. In the infinite window setting, we present algorithms for frequency estimation, heavy hitters, and count-min sketch. For both the infinite window and sliding window settings, our parallel algorithms process a "minibatch" of items using linear work and polylog parallel depth. We also prove a lower bound showing that the work of the parallel algorithm is optimal in the case of heavy hitters and frequency estimation. To our knowledge, these are the first parallel algorithms for these problems that are provably work e fficient and have low depth.

关键词： parallel streaming stream processing heavy hitter basic counting

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Exploring the Design Space of SPMD Divergence Management on Data-parallel architectures 47

Exploring the Design Space of SPMD Divergence Management on ...

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47th Annual IEEE/acm International symposium on Microarchitecture (MICRO)

作者： Lee, Yunsup Grover, Vinod Krashinsky, Ronny Stephenson, Mark Keckler, Stephen W. Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA NVIDIA Santa Clara CA USA Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781479969982

Data-parallel architectures must provide efficient support for complex control-flow constructs to support sophisticated applications coded in modern single-program multiple-data languages. As these architectures have wide datapaths that process a single instruction across parallel threads, a mechanism is needed to track and sequence threads as they traverse potentially divergent control paths through the program. the design space for divergence management ranges from software-only approaches where divergence is explicitly managed by the compiler, to hardware solutions where divergence is managed implicitly by the microarchitecture. In this paper, we explore this space and propose a new predication-based approach for handling control-flow structures in data-parallel architectures. Unlike prior predication algorithms, our new compiler analyses and hardware instructions consider the commonality of predication conditions across threads to improve efficiency. We prototype our algorithms in a production compiler and evaluate the tradeoffs between software and hardware divergence management on current GPU silicon. We show that our compiler algorithms make a predication-only architecture competitive in performance to one with hardware support for tracking divergence.

关键词： Vectors Hardware Computer architecture Registers Optimization Software Support vector machines

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Brief Announcement: Faster 3-Periodic Merging Networks

Brief Announcement: Faster 3-Periodic Merging Networks

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26th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Piotrow, Marek Univ Wroclaw Inst Comp Sci PL-50383 Wroclaw Poland

ISBN: (纸本)9781450328210

We consider the problem of merging two sorted sequences on a comparator network that is used repeatedly, that is, if the output is not sorted, the network is applied again using the output as input. the challenging task is to construct such networks of small depth (called a period in this context). the first constructions of merging networks with a constant period were described by Kutylowski et al. they gave 3-periodic network that merges two sorted sequences of N numbers in time 12 log N and a similar network of period 4 that works in 5.67 log N. We present a new family of 3-periodic merging networks with merging time upper-bounded by 6 log N. the construction can be easily generalized to larger constant periods with decreasing running time, for example, to 4-periodic ones that work in time upper-bounded by 4 log N

关键词： parallel merging oblivious merging merging network comparator

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Ordering Heuristics for parallel Graph Coloring 14

Ordering Heuristics for Parallel Graph Coloring

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26th acm symposium on parallelism in algorithms and architectures (SPAA)

作者： Hasenplaugh, William Kaler, Tim Schardl, Tao B. Leiserson, Charles E. MIT Comp Sci & Artificial Intelligence Lab 32 Vassar St Cambridge MA 02139 USA

ISBN: (纸本)9781450328210

this paper introduces the largest-log-degree-first (LLF) and smallest-log-degree-last (SLL) ordering heuristics for parallel greedy graph-coloring algorithms which are inspired by the largest-degree-first (LF) and smallest-degree-last (SL) serial heuristics respectively. We show that although LF and SL in practice generate colorings with relatively small numbers of colors they are vulnerable to adversarial inputs for which any parallelization yields a poor parallel speedup. In contrast LLF and SLL allow for provably good speedups on arbitrary inputs while in practice producing colorings of competitive quality to their serial analogs. We applied LLF and SLL to the parallel greedy coloring algorithm introduced by Jones and Plassmann referred to here as JP. Jones and Plassman analyze the variant of JP that processes the vertices of a graph in a random order and show that on an O(1)-degree graph G = (V E) this JP-R variant has an expected parallel running time of O(lgV / lg lgV) in a PRAM model. We improve this bound to show using work-span analysis that JP-R augmented to handle arbitrary-degree graphs colors a graph G = (V E) with degree Delta using theta(V + E) work and O(lgV + lg Delta {min root Epsilon, Delta+ lg Delta lgV = lglgV} expected span. We prove that JP-LLF and JP-SLL JP using the LLF and SLL heuristics respectively execute with the same asymptotic work as JP-R and only logarithmically more span while producing higher-quality colorings than JP-R in practice. We engineered an efficient implementation of JP for modern shared-memory multicore computers and evaluated its performance on a machine with 12 Intel Core-i7 (Nehalem) processor cores. Our implementation of JP-LLF achieves a geometric-mean speedup of 7 :83 on eight real-world graphs and a geometric-mean speedup of 8:08 on ten synthetic graphs while our implementation using SLL achieves a geometric-mean speedup of 5:36 on these real-world graphs and a geometric-mean speedup of 7:02 on these synthetic gr

关键词： parallel algorithms graph coloring ordering heuristics Cilk

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parallel Subgraph Counting for Multicore architectures 12

Parallel Subgraph Counting for Multicore Architectures

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12th IEEE International symposium on parallel and Distributed Processing with Applications (ISPA)

作者： Aparicio, David Ribeiro, Pedro Silva, Fernando Univ Porto CRACS P-4169007 Oporto Portugal Univ Porto INESC TEC LA Fac Ciencias P-4169007 Oporto Portugal

ISBN: (纸本)9781479942930

Computing the frequency of small subgraphs on a large network is a computationally hard task. this is, however, an important graph mining primitive, with several applications, and here we present a novel multicore parallel algorithm for this task. At the core of our methodology lies a state-of-the-art data structure, the g-trie, which represents a collection of subgraphs and allows for a very efficient sequential search. Our implementation was done using Pthreads and can run on any multicore personal computer. We employ a diagonal work sharing strategy to dynamically and effectively divide work among threads during the execution. We assess the performance of our Pthreads implementation on a set of representative networks from various domains and with diverse topological features. For most networks, we obtain a speedup of over 50 for 64 cores and an almost linear speedup up to 32 cores, showcasing the flexibility and scalability of our algorithm. this paves the way for the usage of such counting algorithms on larger subgraph and network sizes without the obligatory access to a cluster.

关键词： parallel algorithms Adaptive Load Balancing Complex Networks Graph Mining G-Tries

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