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Euromicro symposium on Digital System Design

作者： Fabrizio Vacca Guido Masera Hazem Moussa Amer Baghdadi Michel Jezequel CERCOM Dipartimento di Elettronica Politecnico di Torino Torino Italy TELECOM Bretagne Electronics Department Technopole Brest-Iroise Brest France

this paper explores the possibility of building a flexible Low Density Parity Check (LDPC) decoder using a network on chip communication infrastructure. Even if this idea is not completely new, previously published works suffered from an excessive area occupation and their practical impact has been very limited. In the following we analyze two possible NOCs specifically designed for the LDPC case. From synthesis results it can be observed how the proposed networks outperform previous implementations in terms of active area with no significant bandwidth loss. Finally to prove the effectiveness of the proposed approach a complete, partially parallel LDPC decoder design is presented and characterized in terms of throughput and area occupation.

关键词： Parity check codes Network-on-a-chip Iterative decoding Iterative algorithms Network synthesis Hardware Routing Equations Message passing Digital systems

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Run-Time Reconfigurable Array Using Magnetic RAM

Run-Time Reconfigurable Array Using Magnetic RAM

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Euromicro symposium on Digital System Design

作者： Victor Silva Luis B. Oliveira Jorge R. Fernandes Mario P. Vestias Horacio C. Neto INESC-ID IST UTL Technical University of Lisbon Portugal INESC-ID FCT UNL New University of Lisbon Portugal INESC-ID ISEL IPL Polytechnic Institute of Lisbon Portugal

this paper presents the implementation of a coarse-grained magnetic RAM based reconfigurable array. the reconfigurable array architecture is organized as a one-dimensional array of programmable ALU, with the configuration bits stored in magnetic random-access memories. the use of MRAM technology to implement run-time reconfigurable hardware devices is a very promising technological solution because MRAM can provide non-volatility with cell areas and access speeds comparable to those of SRAM, and with lower process complexity than flash memory. this type of coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit larger amounts of operation-level parallelism than common fine-grained architectures. By substantially reducing the overhead for configurability, this coarse-grain architecture is also more apt to efficiently exploit run-time reconfiguration and therefore to take advantage of multi-context MRAM-based configuration memories.

关键词： Runtime Magnetic tunneling Random access memory Computer architecture Field programmable gate arrays Programmable logic arrays Read-write memory Hardware parallel processing Fabrics

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Tight Competitive Ratios for parallel Disk Prefetching and Caching 08

Tight Competitive Ratios for Parallel Disk Prefetching and C...

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20th acm symposium on parallelism in algorithms and architectures

作者： Hon, Wing-Kai Shah, Rahul Varman, Peter J. Vitter, Jeffrey Scott Natl Tsing Hua Univ Dept Comp Sci Hsinchu Taiwan Louisiana State Univ Dept Comp Sci Baton Rouge LA 70803 USA Rice Univ Dept ECE Houston TX 77251 USA Purdue Univ Coll Sci W Lafayette IN 47907 USA

ISBN: (纸本)9781595939739

We consider the natural extension of the well-known single disk caching problem to the parallel disk I/O model (PDM) [17]. the main challenge is to achieve as much parallelism as possible and avoid I/O bottlenecks. We are given a fast memory (cache) of size M memory blocks along with a request sequence Sigma = (b(1),b(2), ... ,b(n)) where each block b(i) resides on one of D disks. In each parallel I/O step, at most one block from each disk can be fetched. the task is to serve Sigma in the minimum number of parallel I/Os. thus, each I/O is analogous to a page fault. the difference here is that during each page fault, up to D blocks can be brought into memory, as long as all of the new blocks entering the memory reside on different disks. the problem has a long history [18, 12, 13, 26]. Note that this problem is non-trivial even if all requests in Sigma are unique. this restricted version is called read-once. Despite the progress in the offline version [13, 15] and read-once version [12], the general online problem still remained open. Here, we provide comprehensive results with a full general solution for the problem with asymptotically tight competitive ratios. To exploit parallelism, any parallel disk algorithm needs a certain amount of lookahead into future requests. To provide effective caching, an online algorithm must achieve o(D) competitive ratio. We show a lower bound that states, for lookahead L <= M, any online algorithm must be Omega(D)-competitive. For lookahead L greater than M(1 + 1/epsilon), where c is a constant, the tight upper bound of O(root MD/L) on competitive ratio is achieved by our algorithm SKEW. the previous algorithm tLRU [26] was O((MD/L)(2/3)) competitive and this was also shown to be tight [26] for an LRU-based strategy. We achieve the tight ratio using a fairly different strategy than LRU. We also show tight results for randomized algorithms against oblivious adversary and give an algorithm achieving better bounds in the resource augme

关键词： Online algorithms Competitive Analysis parallel Disk Model

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Benchmarking of PENTRAN-SSN parallel transport code and FAST preconditioning algorithm using the VENUS-2 MOX-fueled benchmark problem

Benchmarking of PENTRAN-SSN parallel transport code and FAST...

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12th International symposium on Reactor Dosimetry

作者： Longoni, Gianluca Haghighat, Alireza Yi, Ce Sjoden, Glenn E. Westinghouse Elect Co LLC POB 158 Interstate 70 Exit 57 Madison PA 15663 USA Univ Florida Nucl & Radiol Engn Gainesville FL 32611 USA

ISBN: (纸本)9780803134126

the discrete ordinates method (Sn) is the most widely used technique to obtain numerical solutions of the linear Boltzmann equation, and therefore to evaluate radiation fields and dose rates in nuclear devices. However, it is well known that this method suffers from slow convergence for problems characterized by optically thick media and scattering ratio close to unity. To address this issue we have developed a new preconditioning algorithm based on the even-parity simplified Sn (EP-SSN) equations. the new method is based on the flux acceleration simplified transport (FAST) algorithm which is implemented into the PENTRAN-SSN code system. the code system is designed for parallel computing architectures;PENTRAN-SSN features spatial, angular, and energy domain decomposition algorithms. the FAST preconditioner is parallelized with a spatial domain decomposition algorithm. In this paper, our objective is to test the performance of the new preconditioning system for a three-dimensional shielding calculation based on the VENUS-2 MOX-fueled benchmark problem, issued by OECD/NEA (Organization for Economic Co-operation and Develpment/Nuclear Energy Agency.

关键词： VENUS benchmark parallel computing radiation transport

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Lightweight cnsistency enforcement schemes for distributed proofs with hidden subtrees

Lightweight cnsistency enforcement schemes for distributed p...

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SacmAT'07: 12th acm symposium on Access Control Models and Technologies

作者： Lee, Adam J. Minami, Kazuhiro Winslett, Marianne Department of Computer Science University of Illinois at Urbana-Champaign Urbana IL 61801

ISBN: (纸本)1595937455

In distributed proof construction systems, information release policies can make it unlikely that any single node in the system is aware of the complete structure of any particular proof tree. this property makes it difficult for queriers to determine whether the proofs constructed using these protocols sampled a consistent snapshot of the system state;this has previously been shown to have dire consequences in decentralized authorization systems. Unfortunately, the consistency enforcement solutions presented in previous work were designed for systems in which only information encoded in certificates issued by certificate authorities is used during the decision-making process. Further, they assume that each piece of certified evidence used during proof construction is available to the decision-making node at runtime. In this paper, we generalize these previous results and present lightweight mechanisms through which consistency constraints can be enforced in proof systems in which the full details of a proof may be unavailable to the querier and the existence of certificate authorities for certifying evidence is unlikely;these types of distributed proof systems are likely candidates for use in pervasive computing and sensor network environments. We present modifications to one such distributed proof system that enable two types of consistency constraints to be enforced while still respecting the same confidentiality and integrity policies as the original proof system. Further, we detail a performance analysis that illustrates the modest overheads of our consistency enforcement schemes. Copyright 2007 acm.

关键词： parallel algorithms

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parallel Lempel Ziv coding

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DISCRETE APPLIED MAthEMATICS 2005年第2期146卷 180-191页

作者： Klein, ST Wiseman, Y Bar Ilan Univ Dept Comp Sci IL-52900 Ramat Gan Israel

We explore the possibility of using multiple processors to improve the encoding and decoding times of Lempel-Ziv schemes. A new layout of the processors, based on a full binary tree, is suggested and it is shown how LZSS and LZW can be adapted to take advantage of such parallel architectures. the layout is then generalized to higher order trees. Experimental results show an improvement in compression over the standard method of parallelization and an improvement in time over the sequential method. (C) 2004 Elsevier B.V. All rights reserved.

关键词： data compression Lempel-Ziv algorithms parallel algorithms

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parallel Lempel Ziv coding

Parallel Lempel Ziv coding

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12th Annual symposium on Combinatorial Pattern Matching (CPM 2001)

作者： Klein, ST Wiseman, Y Bar Ilan Univ Dept Comp Sci IL-52900 Ramat Gan Israel

关键词： data compression Lempel-Ziv algorithms parallel algorithms

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Multi-word atomic read/write registers on multiprocessor systems

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12th Annual European symposium on algorithms, ESA 2004

作者： Larsson, Andreas Gidenstam, Anders Ha, Phuong H. Papatriantafilou, Marina Tsigas, Philippas Department of Comp. Science Chalmers University of Technology GöteborgSE-412 96 Sweden

ISBN: (纸本)3540230254

Modern multiprocessor systems offer advanced synchronization primitives, built in hardware, to support the development of efficient parallel algorithms. In this paper we develop a simple and efficient algorithm for atomic registers (variables) of arbitrary length. the simplicity and better complexity of the algorithm is achieved via the utilization of two such common synchronization primitives. In this paper we also evaluate the performance of our algorithm and the performance of a practical previously know algorithm that is based only on read and write primitives. the evaluation is performed on 3 well-known, parallel architectures. this evaluation clearly shows that both algorithms are practical and that as the size of the register increases our algorithm performs better, accordingly to its complexity behavior. © Springer-Verlag Berlin Heidelberg 2004.

关键词： parallel architectures

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A single program multiple data parallel processing platform for FPGAs

A single program multiple data parallel processing platform ...

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Annual IEEE symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： P. James-Roxby P. Schumacher C. Ross Xilinx Research Laboratories Longmont CO USA Colorado State University Fort Collins CO USA

the prevalence of software reference code motivates investigation into efficient implementations of software architectures on field-programmable devices. Modern FPGAs allow designers to generate multi-processor architectures that exactly match the processing needs of the algorithm. this paper describes an architecture supporting the single program multiple data model of parallel processing, and presents results taken from a parallel implementation of the JPEG2000 encoding algorithm and Mandelbrot set generation.

关键词： parallel processing Field programmable gate arrays Algorithm design and analysis Software algorithms Computer architecture Hardware Color Discrete wavelet transforms Reduced instruction set computing Software architecture

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Optimal schedules for cycle-stealing in a network of workstations with a bag-of-tasks workload

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2002年第2期13卷 179-191页

作者： Rosenberg, AL Univ Massachusetts Dept Comp Sci Amherst MA 01003 USA

We refine the model underlying our prior work on scheduling bag-of-tasks ("embarrassingly parallel") workloads via cycle-stealing In networks of workstations [5], [17], obtaining a model wherein the scheduling guidelines of [17] produce optimal schedules for every such cycle-stealing opportunity. We thereby render prescriptive the descriptive model of those sources. Although computing optimal schedules usually requires the use of general function-optimizing methods, we show how to compute optimal schedules efficiently for the broad class of opportunities whose durations come from a concave probability distribution. Even when no such efficient computation of an optimal schedule is available, our refined model often suggests a natural notion of approximately optimal schedule, which may be efficiently computable. We illustrate such efficient approximability via the important class of cycle-stealing opportunities whose durations come from a heavy-tailed distribution. Such opportunities do not admit any optimal schedule-nor even a natural notion of approximately optimal schedule-within the model of [5], [17]. Within our refined model, though, we derive computationally simple schedules for heavy-tailed opportunities, which can be "tuned" to accomplish an expected amount of work that is arbitrarily close to optimal.

关键词： cycle-stealing bag-of-tasks workloads heavy-tailed distributions networks of workstations (NOWs) optimal scheduling scheduling parallel computations

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