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检索条件"任意字段=12th Euromicro Conference on Parallel, Distributed and Network-Based Processing"

共 1249 条记录，以下是101-110 订阅

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Efficient NAS parallel Benchmark Kernels with CUDA 28

Efficient NAS Parallel Benchmark Kernels with CUDA

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： de Araujo, Gabriell Alves Griebler, Dalvan Danelutto, Marco Fernandes, Luiz Gustavo Pontifical Catholic Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Tres De Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Univ Pisa UNIPI Comp Sci Dept Pisa Italy

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

NAS parallel Benchmarks (NPB) are one of the standard benchmark suites used to evaluate parallel hardware and software. there are many research efforts trying to provide different parallel versions apart from the original OpenMP and MPI. Concerning GPU accelerators, there are only the OpenCL and OpenACC available as consolidated versions. Our goal is to provide an efficient parallel implementation of the five NPB kernels with CUDA. Our contribution covers different aspects. First, best parallel programming practices were followed to implement NPB kernels using CUDA. Second, the support of larger workloads (class B and C) allow to stress and investigate the memory of robust GPUs. third, we show that it is possible to make NPB efficient and suitable for GPUs although the benchmarks were designed for CPUs in the past. We succeed in achieving double performance with respect to the state-of-theart in some cases as well as implementing efficient memory usage. Fourth, we discuss new experiments comparing performance and memory usage against OpenACC and OpenCL state-of-the-art versions using a relative new GPU architecture. the experimental results also revealed that our version is the best one for all the NPB kernels compared to OpenACC and OpenCL. the greatest differences were observed for the FT and EP kernels.

关键词： Graphics processing units Kernel Benchmark testing Programming Computer architecture Hardware Standards

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Evaluating the performance and improving the usability of parallel and distributed Word Embeddings tools 28

Evaluating the performance and improving the usability of pa...

引用

28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： da Silva, Matheus L. Meyer, Vinicius Kirchoff, Dionatra F. Nero, Joaquim F. S. Vieira, Renata De Rose, Cesar A. F. Pontific Catholic Univ Rio Grande PUCKS Polytech Sch Ipiranga Ave 6681 BR-90619900 Porto Alegre RS Brazil

ISBN: (纸本)9781728165820

the representation of words by means of vectors, also called Word Embeddings (WE), has been receiving great attention from the Natural Language processing (NLP) field. WE models are able to express syntactic and semantic similarities, as well as relationships and contexts of words within a given corpus. Although the most popular implementations of WE algorithms present low scalability, there are new approaches that apply High-Performance Computing (HPC) techniques. this is an opportunity for an analysis of the main differences among the existing implementations, based on performance and scalability metrics. In this paper, we present a study which addresses resource utilization and performance aspects of known WE algorithms foetid in the literature. To improve scalability and usability we propose a wrapper library for local and remote execution environments that contains a set of optimizations such as the pWord2vec, pWord2vec_MPI, Wang2vec and the original Word2vec algorithm. Utilizing these optimizations it is possible to achieve an average performance gain of 15x for multicores and 105x for multinodes compared to the original version. there is also a big reduction in the memory footprint compared to the most popular python versions.

关键词： Natural Language processing Word2vec Performance Evaluation

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Lessons learned from comparing C-CUDA and Python-Numba for GPU-Computing 28

Lessons learned from comparing C-CUDA and Python-Numba for G...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Oden, Lena Fernuniv Inst Math & Informat Hagen Germany

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

Python as programming language is increasingly gaining importance, especially in data science, scientific, and parallel programming. It is faster and easier to learn than classical programming languages such as C. However, usability often comes at the cost of performance and applications written in Python are considered to be much slower than applications written in C or FORTRAN. Further, it does not allow the usage of CPUs-besides of pre-compiled libraries. However, the Numba package promises performance similar to C code for compute intensive parts of a Python application and it supports CUDA, which allows the use of GPUs inside a Python application. In this paper we compare the perforinance of iVumba-CUDA and C-CUDA for different kinds of applications. For compute intensive benchmarks, the performance of the Numba version only reaches between 50% and 85% performance of the CCUDA version, despite the reduction operation, where the Numba version outperforms CUDA. Analyzing the PTX code and CUDA performance counters revealed that index-calculation is one 'uniting factor in Numba. Another problem is the type interference for single precision computations, as sonic values are computed in double precision. By optimizing this within the Numba package, the performance of Numba improves. However, C-CUDA applications still outperform the Numba versions. Further analysis with the CloverLeav Mini App shows that Numba performance further decreases for applications with multiple different compute kernels. the non-CPU part slows down these applications, due to the slow Python interpreter. this leads to a worse GPU utilization.

关键词： Python Graphics processing units Libraries Kernel Indexes Benchmark testing

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Designing 64-Bit LUT based FFT Structure for High-Speed DSP Applications

Designing 64-Bit LUT based FFT Structure for High-Speed DSP ...

引用

International conference on Communication Systems and network Technologies (CSNT)

作者： M. Bharathi G. Amrutha Sai B. Divya Sree K Bharadwaj Karthik B. Uday Kiran Naik Yasha Jyothi Shirur VTU & Electronics and Communication Engineering Mohan Babu University Tirupati Andhra Pradesh India Electronics and Communication Engineering Mohan Babu University Tirupati Andhra Pradesh India Electronics and Communication Engineering BNM Institute of Technology Bangalore India

Digital signal processing (DSP) utilizes the efficient Fast Fourier Transform (FFT) Methodology that is used to alter, filter, and decode digital audio, video, and image data. FFT is used to design Electrical Circuits, to solve differential equations, to analyze signals and to process images. distributed Arithmetic (DA) is a multiplier-less implementation technique that computes the inner dot product between two signals-fixed and varying by using shifters and adders. It takes the values in a bit-serial fashion which suits for real-time processing. the Computation Logic Blocks (CLBs) of Field Programmable Gate Anays (FPGAs) Utilize distributed Arithmetic. FFT can be calculated using the DA method. the existing method to calculate FFT is based on complex multiplications and additions which consume time as well as power. Hence DA based FFT has been proposed in which the delay is 29.3% less and the power is 21.8% less than that of the existing method.

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Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design through Constraint Programming 28

Temperature-Aware Core Mapping for Heterogeneous 3D NoC Desi...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Derniriz, Ayhan Ahangari, Hamzeh Ozturk, Ozcan Gebze Tech Univ TR-41400 Kocaeli Turkey Bilkent Univ TR-06800 Ankara Turkey

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165820

In the context of network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance and power consuinption. Moreover, in emerging 3D NoC systems, by intensification of cooling issues, temperature constraints on hot-spots are added, and problem becomes more complicated. In this paper, an earlier Constraint Programming (('P) methodology for heterogeneous 2D NoC design is extended to 3D model, while critical temperature constraints are accounted. In a single stage, our approach can choose core types from a set of low, medium and high power, and assign them to appropriate places on the mesh which minimizes the overall computation time and communication cost while satisfying the temperature constraints. To achieve our objective, in addition to cores placement problem, tasks should also be scheduled on corresponding cores with matching performance levels to minimize the overall completion time (makespan). Experimental results show that task completion times are more dependent on the mesh structure for our benchmark data. 3D mesh structures may yield shorter task completion times, without compromising thermal constraints. On the other hand, restricting the peak temperature naturally requires the usage of low-performance computing elements which inherently may delay the processing time.

关键词： network-on-Chip 3D Integration Heterogeneous Core Mapping Task Scheduling Constraint Programming

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ZePoP: A distributed Leader Election Protocol using the Delay-based Closeness Centrality for Peer-to-Peer Applications

ZePoP: A Distributed Leader Election Protocol using the Dela...

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IEEE International conference on Cloud networking (CLOUDNET)

作者： Md Amjad Hossain Javed I. Khan School of Business and Technology Emporia State University Emporia KS Department of Computer Science Kent State University Kent OH

this paper presents ZePoP, a leader election protocol for distributed systems, optimizing a delay-based closeness centrality. We design the protocol specifically for the Peer to Peer(P2P) applications, where the leader peer (node) is responsible for collecting, processing, and redistributing data or control signals satisfying some timing constraints. the protocol elects an optimal leader node in the dynamically changing network and constructs a Data Collection and Distribution Tree (DCDT) rooted at the leader node. the elected optimal leader is closest to all nodes in the system compared to other nodes. We validate the proposed protocol through theoretical proofs as well as experimental results.

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An Interference-Aware Application Classifier based on Machine Learning to Improve Scheduling in Clouds 28

An Interference-Aware Application Classifier Based on Machin...

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28th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Meyer, Vinicius Kirchoff, Dionatra F. da Silva, Matheus L. De Rose, Cesar A. F. Pontifical Catholic Univ Rio Grande Sul PUCRS Polytech Sch Porto Alegre RS Brazil

ISBN: (纸本)9781728165820

To maximize resource utilization and system throughput in cloud platforms, hardware resources are often shared across multiple virtualized services or applications. In such a consolidated scenario, performance of applications running concurrently in the same physical host can be negatively affected due to interference caused by resource contention. this should be taken into account for efficient scheduling of such applications and performance prediction at user level. Nevertheless, resource scheduling in cloud computing is usually based solely on resource capacity, implemented by heuristics such as bin-packing. Our previous work has introduced an interference aware scheduling model for web -applications considering their resource utilization profile, and to classify applications we applied fixed interference intervals based on common utilization patters. Although this resulted in placements with better overall results, we observed that some applications with more dynamic workload patterns were wrongly classified with intervals. In this paper, we propose an alternative to the use of intervals and present an interference -aware application classifier for cloud based applications that deals better with dynamic workloads. Our classifier defines automatically interference levels ranges combining two well-known machine learning techniques: Support Vector Machines and K-Means. Preliminary experiments evaluated the applied machine learning techniques in three quality metrics: Accuracy, Fl -Score and Rand Index, observing rates over 80%. the proposed solution creates a workload -aware finegrained classification that was compared with previous work over different workload scenarios. the results demonstrate that our classification approach improves the placement efficiency by 23% on average.

关键词： Interference-Aware Application Classifier Resource Management Dynamic Workloads

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Novel Cyber Incident Management System for 5G-based Critical Infrastructures 12

Novel Cyber Incident Management System for 5G-based Critical...

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12th IEEE International conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS 2023

作者： Polozhentsev, Artem Gnatyuk, Sergiy Berdibayev, Rat Sydorenko, Viktoriia Zhyharevych, Oksana National Aviation University Kyiv Ukraine Yessenov University Aktau Kazakhstan State Scientific and Research Institute of Cybersecurity Technologies and Information Protection Kyiv Ukraine Almaty University of Power Energy and Telecommunication Almaty Kazakhstan Lesya Ukrainka Volyn National University Lutsk Ukraine

ISBN: (纸本)9798350358056

Modern critical infrastructure with diverse systems requires a security information and event management (SIEM) system for unified monitoring against cyber threats. this system collects log data, performs real-time analysis, flags threats, triggers alerts, and advises response strategies. Enhanced by AI, Internet of things, and cloud technologies, modern SIEM systems have significantly improved and optimized threat detection. this research examines the functionality, basic operation, and comparative capabilities of current SIEM systems. In addition, a universal event correlation and cybersecurity incident management system was designed and studied specifically for 5G networks. Hybrid security data storage models were also developed to ensure fast search, scale with data volume, and interface with external storage. the research also formulated models for distributed data bus operation, which enables fast processing of large data streams with minimal latency and high resilience. the proposed system addresses key cybersecurity challenges and meets global standards for establishing cyber incident management systems in 5G-based critical infrastructure. © 2023 IEEE.

关键词： 5G-based critical infrastrucute cyber security cyber threats SIEM

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Implementation and Evaluation of CYPHONIC client focusing on Sequencing mechanisms and Concurrency for packet processing

Implementation and Evaluation of CYPHONIC client focusing on...

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IEEE Global conference on Consumer Electronics (GCCE)

作者： Ren Goto Kazushige Matama Ryouta Aihata Shota Horisaki Hidekazu Suzuki Katsuhiro Naito Aichi Institute of Technology Toyota Japan Meijo University Nagoya Japan

Peer-to-Peer (P2P) based direct communication among devices can enhance communication speed and reduce the burden on cloud services in service models involving distributed and cooperative processing. the authors have proposed and developed CYber PHysical Overlay network over Internet Communication (CYPHONIC), which offers a secure communication mechanism based on a P2P model. However, the performance of conventional CYPHONIC clients is limited because they process packets in a single-threaded manner, considering the simplicity of sequential packet processing. this paper presents a redesigned implementation of the CYPHONIC client that supports multi-threaded packet processing. the new client design incorporates a novel processing scheme that emphasizes sequencing mechanisms and concurrency in packet processing, as the order of packet processing is not guaranteed in multi-threaded processing. these improvements have significantly increased end-node throughput and enabled communication delay times to remain constant even as the number of connections increases.

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Implementation of IEEE1588 Protocol based on STM32H750

Implementation of IEEE1588 Protocol Based on STM32H750

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Information and Communication Technology (ICTech), International conference of

作者： XinFei Xiong Fang He Yan Li WenZe Han YanFei Jiao Shenyang Institute of Computing Technology Chinese Academy of Sciences Shengyang China University of Chinese Academy of Sciences Beijing China

In the industrial control field, multiple nodes in the network need to collect and process data cooperatively. However, due to the lack of clock synchronization capability of the network, the data lacks time series information, which will lead to the abnormal fusion processing of multiple data by the upper computer, In the system, IEEE1588 protocol (accurate clock synchronization protocol of network measurement and control system) is used to solve the above problems. based on the development board with STM32H750 microcontroller as the core, a distributed clock synchronization system is built. the system has built a LwIP (Light Weight TCP/IP Stack) network protocol stack to realize the transmission of various messages during clock synchronization, the time jitter delay from the transmission layer of the network protocol stack to the framing of the data link layer is eliminated, and the accuracy of clock synchronization is improved. the experimental results show that the system can achieve nanosecond level clock synchronization, and can be used in industrial control sites that require high real-time performance.

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