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检索条件"任意字段=12th Euromicro Conference on Parallel, Distributed and Network-Based Processing"

共 1249 条记录，以下是131-140 订阅

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Towards On-the-fly Self-Adaptation of Stream parallel Patterns

Towards On-the-fly Self-Adaptation of Stream Parallel Patter...

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euromicro conference on parallel, distributed and network-based processing

作者： Adriano Vogel Gabriele Mencagli Dalvan Griebler Marco Danelutto Luiz Gustavo Fernandes School of Technology Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil University of Pisa (UNIPI) Pisa Italy Laboratory of Advanced Research on Cloud Computing (LARCC) Tres de Maio Faculty (SETREM) Três de Maio Brazil

ISBN: (纸本)9781665414555;9781665447645

Stream processing applications compute streams of data and provide insightful results in a timely manner, where parallel computing is necessary for accelerating the application executions. Considering that these applications are becoming increasingly dynamic and long-running, a potential solution is to apply dynamic runtime changes. However, it is challenging for humans to continuously monitor and manually self-optimize the executions. In this paper, we propose self-adaptiveness of the parallel patterns used, enabling flexible on-the-fly adaptations. the proposed solution is evaluated with an existing programming framework and running experiments with a synthetic and a real-world application. the results show that the proposed solution is able to dynamically self-adapt to the most suitable parallel pattern configuration and achieve performance competitive with the best static cases. the feasibility of the proposed solution encourages future optimizations and other applicabilities.

关键词： Runtime Programming parallel processing Acceleration Optimization Monitoring

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Application Characterization for Near Memory processing

Application Characterization for Near Memory Processing

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euromicro conference on parallel, distributed and network-based processing

作者： Maryam S. Hosseini Masoumeh Ebrahimi Pooria Yaghini Nader Bagherzadeh Center for Pervasive Communications and Computing (CPCC) University of California Irvine KTH Royal Institute of Technology Sweden

Data movement between memory subsystem and processor unit is a crippling performance and energy bottleneck for data-intensive applications. Near Memory processing (NMP) is a promising solution to alleviate the data movement bottleneck. the introduction of 3D-stacked memories and more importantly hybrid memory systems enable the long-wished NMP capability. this work explores the feasibility and efficacy of having NMP on the hybrid memory system for a given set of applications. In this paper, we first redefine a set of NMP-centric performance metrics in order to analyze the efficacy of a given processing unit. Leveraging the proposed metrics, we characterize various sets of applications to assess the suitability of a processing unit in terms of performance. Specifically, in this work we motivate the efficiency of NMP subsystems to process memory-intensive applications when 3D-NVM technologies are employed.

关键词： Measurement Nonvolatile memory Memory management Performance analysis Central processing Unit

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Introducing a Stream processing Framework for Assessing parallel Programming Interfaces

Introducing a Stream Processing Framework for Assessing Para...

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euromicro conference on parallel, distributed and network-based processing

作者： Adriano Marques Garcia Dalvan Griebler Luiz G. L. Fernandes Claudio Schepke School of Technology Pontifical Catholic University of Rio Grande do Sul (PUCRS) Porto Alegre Brazil Laboratory of Advanced Research on Cloud Computing (LARCC) Três de Maio Maio Faculty (SETREM) Três de Maio Brazil Federal University of Pampa (UNIPAMPA) Alegrete Brazil

Stream processing applications are spread across different sectors of industry and people's daily lives. the increasing data we produce, such as audio, video, image, and text are demanding quickly and efficiently computation. It can be done through Stream parallelism, which is still a challenging task and most reserved for experts. We introduce a Stream processing framework for assessing parallel Programming Interfaces (PPIs). Our framework targets multi-core architectures and C++ stream processing applications, providing an API that abstracts the details of the stream operators of these applications. therefore, users can easily identify all the basic operators and implement parallelism through different PPIs. In this paper, we present the proposed framework, implement three applications using its API, and show how it works, by using it to parallelize and evaluate the applications with the PPIs Intel TBB, FastFlow, and SPar. the performance results were consistent with the literature.

关键词： Industries parallel programming distributed databases Computer architecture Streaming media parallel processing Task analysis

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Local Traffic-based Energy-Efficient Hybrid Switching for On-Chip networks

Local Traffic-Based Energy-Efficient Hybrid Switching for On...

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euromicro conference on parallel, distributed and network-based processing

作者： Yuan He Jinyu Jiao Masaaki Kondo Shenyang University of Technology Liaoning China The University of Tokyo Tokyo Japan RIKEN Center for Computational Science Kobe Japan

Advanced flow control mechanisms employed by modern on-chip networks are the reasons of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power and offer an end-to-end latency analogous to wire delay. In this paper, we present a hybrid flow control mechanism, which mixes both virtual channels and circuit-switching, to provide a latency-competitive and energy-efficient on-chip network design. Contrary to existing hybrid switching designs, our proposal is based on local traffic so that circuits are formed without the knowledge of end-to-end traffic. When compared to on-chip networks with virtual channels, our proposal achieves a very competitive latency per flit, for up to 4% lower, while also dramatically suppressing the energy per flit by up to 18%.

关键词： Wires Switches Control systems Energy efficiency System-on-chip Delays Proposals

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Combining thread throttling and Mapping to Optimize the EDP of parallel Applications

Combining Thread Throttling and Mapping to Optimize the EDP ...

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euromicro conference on parallel, distributed and network-based processing

作者： Gustavo P. Berned thiarles S. Medeiros Matheus Serpa Fábio D. Rossi Marcelo C. Luizelli Philippe O. Navaux Antonio Carlos S. Beck Arthur F. Lorenzon Federal University of Pampa - Campus Alegrete Brazil Institute of Informatics - Federal University of Rio Grande do Sul Brazil Science and Technology Farroupilha Federal Institute of Education Brazil

thread-throttling and mapping strategies have been used together to make better use of hardware resources and improve the energy-delay product (EDP) of high-performance computing (HPC) systems. However, the design space exploration significantly grows with the increasing number of cores in those systems, making the task of finding the ideal number of active threads and allocating strategy a challenging task. On top of that, parallel applications present various patterns, such as irregularity, unbalanced computations, or high rates of communications. Given these considerations, we propose ETTM, an EDPaware thread-throttling and mapping optimization strategy that automatically finds an ideal combination of number of threads and thread mapping strategy. With the execution of eighteen well-known benchmarks on three multicore architectures, we show that EDP can be significantly improved when running applications with the solution found by EETM¹.

关键词： Multicore processing Instruction sets distributed databases Computer architecture Benchmark testing Hardware Space exploration

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Low-Latency Low-Energy Memory-Cube networks using Dual-Voltage Datapaths

Low-Latency Low-Energy Memory-Cube Networks using Dual-Volta...

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euromicro conference on parallel, distributed and network-based processing

作者： Yoshiya Shikama Ryuta Kawano Hiroki Matsutani Hideharu Amano Yusuke Nagasaka Naoto Fukumoto Michihiro Koibuchi Keio University Japan Advanced Institute of Science and Technology Fujitsu Laboratories Ltd. National Institute of Informatics

three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. the DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

关键词： Low voltage Power demand network topology Memory management Layout Routing throughput

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Reducing Model Cost based on the Weights of Each Layer for Federated Learning Clustering 12

Reducing Model Cost Based on the Weights of Each Layer for F...

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12th International conference on Ubiquitous and Future networks (ICUFN)

作者： Kim, Hyungbin Kim, Yongho Park, Hyunhee Myongji Univ Dept Informat & Commun Engn Yongin South Korea

ISBN: (纸本)9781728164762

Federated Learning (FL) has a different learning framework from existing machine learning, which had to centralize training data. Federated learning has the advantage of protecting privacy because learning is performed on each client device rather than the central server, and only the weight parameter values, which are the learning results, are sent to the central server. However, the performance of federated learning shows relatively low performance compared to cloud computing, and in reality, it is difficult to build a federated learning environment due to the high communication cost between the server and multiple clients. In this paper, we propose Federated Learning with Clustering algorithms (FLC). the proposed FLC is a method of clustering clients with similar characteristics by analyzing the weights of each layer of a machine learning model, and performing federated learning among the clustered clients. the proposed FLC can reduce the communication cost for each model by reducing the number of clients corresponding to each model. As a result of extensive simulation, it is confirmed that the accuracy is improved by 2.4% and the loss by 47% through the proposed FLC compared to the standard federated learning.

关键词： Federated learning distributed machine learning distributed databases distributed processing Clustering algorithms Computational modeling

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High-Performance parallel Fault Simulation for Multi-Core Systems

High-Performance Parallel Fault Simulation for Multi-Core Sy...

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euromicro conference on parallel, distributed and network-based processing

作者： Masoomeh Karami Mohammad-hashem Haghbayan Masoumeh Ebrahimi Hamid Nejatollahi Hannu Tenhunen Juha Plosila University of Turku Turku Finland Royal Institute of Technology (KTH) Kista Sweden. University of California Irvine CA USA.

Fault simulation is a time-consuming process that requires customized methods and techniques to accelerate it. Multi-threading and Multi-core approaches are two promising techniques that can be exploited to accelerate the fault simulation process by using different parts of the hardware at the same time. However, an efficient parallelization is obtained only by the refinement of software with respect to the hardware platform. In this paper, a parallel multi-thread fault simulation technique is proposed to accelerate the simulation process on multi-core platforms. In this approach, the gate input values are independently assigned to each thread. Each input value carries the information of several parallel simulation processes. this provides a multithread parallel fault simulation environment. the experimental results show that the proposed technique can efficiently use the hardware platform. In a single-core platform, the proposed technique can reduce the time by 25% while in a dual-core increasing the thread approximately halves the execution time.

关键词： Multicore processing Instruction sets Very large scale integration Logic gates Hardware Software Circuit faults

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On GPU optimizations of stencil codes for highly parallel simulations

On GPU optimizations of stencil codes for highly parallel si...

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euromicro conference on parallel, distributed and network-based processing

作者： Nikolai Pfisterer Marco Berghoff Achim Streit Steinbuch Centre for Computing Karlsruhe Institute of Technology Karlsruhe Germany

Stencil codes are valuable methods to solve partial differential equations of models in a wide range of applications in science and engineering. Graphics processing units (GPUs) provide a highly parallel architecture with fast directly accessible memory that is desirable to run stencil codes. they enable larger and more complex simulations that are solved faster compared to simulating on CPUs. We provide a solution for users to run highly parallel stencil codes on GPUs, that can also be efficiently used on a distributed GPU *** this work, we present an extension to the multi-disciplinary framework NAStJA originally designed to efficiently run stencil codes on the CPUs in current high-performance computing (HPC) systems, to also be able to run on GPUs. We describe different methods to increase the performance of stencil codes on GPUs like a border exchange method which is transparent to the user, as well as a buffer for gradient values that are needed multiple times. We show their performance using the phase-field method as a stencil code *** this GPU extension and optimizations implemented into the NAStJA framework, we can show highly improved performance compared to the CPU implementation, and an efficiency of 92% (weak scaling) for a large-scale example simulation on 64 GPUs on the ForHLR II HPC system.

关键词： Partial differential equations Graphics processing units Clustering algorithms Performance gain parallel architectures Central processing Unit Mathematical model

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MPEG NBMP testbed for evaluation of real-Time distributed media processing workflows at scale 21

MPEG NBMP testbed for evaluation of real-Time distributed me...

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12th ACM Multimedia Systems conference, MMSys 2021

作者： Ramos-Chavez, Roberto Mekuria, Rufael Karagkioules, theo Griffioen, Dirk Wagenaar, Arjen Ogle, Mark Unified Streaming Amsterdam Netherlands

ISBN: (纸本)9781450384346

Real-Time distributed Media processing Workflows (DMPW) are popular for online media delivery. Combining distributed media sources and processing can reduce storage costs and increase flexibility. However, high request rates may result in unacceptable latency or even failures in incorrect configurations. thus, testing DMPW deployments at scale is key, particularly for real-Time cases. We propose the new MPEG network based Media processing (NBMP) standard for this and present a testbed implementation that includes all the reference components. In addition, the testbed includes a set of configurable functions for load generation, monitoring, data-collection and visualization. the testbed is used to test Dynamic Adaptive HTTP streaming functions under different workloads in a standardized and reproducible manner. A total of 327 tests with different loads and Real-Time DMPW configurations were completed. the results provide insights in the performance, reliability and time-consistency of each configuration. based on these tests, we selected the preferred cloud instance type, considering hypervisor options and different function implementation configurations. Further, we analyzed different processing tasks and options for distributed deployments on edge and centralized clouds. Last, a classifier was developed to detect if failures happen under a certain workload. Results also show that, normalized inter-experiment standard deviation of the metric means can be an indicator for unstable or incorrect configurations. © 2021 ACM.

关键词： Testbeds

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