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Improving Communication and Load Balancing with thread Mapping in Manycore Systems 26

Improving Communication and Load Balancing with Thread Mappi...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Cruz, Eduardo H. M. Diener, Matthias Serpa, Matheus S. Navaux, Philippe O. A. Pilla, Laercio L. Koren, Israel Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Fed Univ Santa Catarina UFSC Informat & Stat Dept Florianopolis SC Brazil Univ Massachusetts Dept Elect Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781538649756

Communication and load balancing have a significant impact on the performance of parallel applications and have been the subject of extensive research in multicore architectures. thread mapping has been one of the solutions adopted in multicore architectures to address both communication and load balancing. However, the impact of such issues on more recently introduced manycore architectures is still unknown. Most related work on manycore architectures focus on execution time and idleness information for scheduling decisions. In this paper, we improve the state of the art by performing a very detailed analysis of the impact of thread mapping on communication and load balancing in two manycore systems from Intel, namely Knights Corner and Knights Landing. We observed that the widely used metric of CPU time provides very inaccurate information for load balancing. We also evaluated the usage of thread mapping based on the communication and load information of the applications to improve the performance of manycore systems.

关键词： Instruction sets Load management Message systems Multicore processing Protocols

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Efficient and Fast Approximate Consensus with Epidemic Failure Detection at Extreme Scale 26

Efficient and Fast Approximate Consensus with Epidemic Failu...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Katti, Amogh Lilja, David J. Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)9781538649756

this paper proposes a memory efficient failure detection and consensus algorithm, for fail-stop type process failures, based on epidemic protocols. It is suitable for extreme scale systems with reliable networks (no message loss) and high failure frequency. Communication time dominates the execution time at scale. the redundant failure detections and non-uniform information dissemination speed of epidemic algorithms make approximate epidemic-based consensus detection a useful way to trade communication overhead for accuracy. An approximate technique to the consensus detection is also proposed in this paper for faster consensus detection. Results show that the algorithm detects consensus correctly on failed processes with logarithmic scalability. the algorithm is tolerant to process failures both before and during the execution and the number of failures (occurring both before and during execution) have virtually no effect on the consensus detection time at scale. Comparison with similar deterministic consensus detection technique shows that the algorithm detects consensus at the same time with high probability. Further, benefits of the proposed approximate technique increase as system size increases. Compared to the non-approximate version, for a system size of 2(18) processes, the communication saved is 34% with accuracy loss of the order of 10(-4) in consensus detection.

关键词： Failure detection Consensus Approximate consensus Communication reduction

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Computing Empirical p-Values for Estimating Gene-Gene Interactions in Genome-Wide Association Studies: a parallel Computing Approach 26

Computing Empirical p-Values for Estimating Gene-Gene Intera...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Giansanti, Valentina D'Agostino, Daniele Maj, Carlo Beretta, Stefano Merelli, Ivan Natl Res Council Italy Inst Appl Math & Informat Technol E Magenes Genoa Italy IRCCS Ist Ctr San Giovanni di Dio Fatebenefratell Genet Unit Brescia Italy Univ Milano Bicocca Dept Informat Syst & Commun Milan Italy Natl Res Council Italy Inst Biomed Technol Segrate MI Italy

ISBN: (纸本)9781538649756

In complex phenotypes (e.g., psychiatric diseases) single locus tests, commonly performed with genome-wide association studies, have proven to be limited in discovering strong gene associations. A growing body of evidence suggests that epistatic non-linear effects may be responsible for complex phenotypes arising from the interaction of different biological factors. A major issue in epistasis analysis is the computational burden due to the huge number of statistical tests to be performed when considering all the potential genotype combinations. In this work, we developed a computational efficient approach to compute empirical p-values concerning the presence of epistasis at a genome-wide scale in bipolar disorder, which is a typical example of complex phenotype with a relevant but unexplained genetic background. By running our approach we were able to identify 13 epistasis interactions between variants located in genes potentially involved in biological processes associated with the analyzed phenotype.

关键词： epistasis empirical p-value parallel computing

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Low-effort task distribution of stencil computation on heterogeneous multi-GPUs: simulating graphene superlattices 26

Low-effort task distribution of stencil computation on heter...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Rodrigues, M. Fernandes, D. Silveirinha, M. Falcao, G. Univ Coimbra Inst Telecomunicacoes Dept Elect & Comp Engn P-3030290 Coimbra Portugal Univ Lsiboa Inst Super Tecn Ave Rovisco Pais 1 P-1049001 Lisbon Portugal

ISBN: (纸本)9781538649756

this paper proposes a low-cost workload distribution technique for the compute-intensive simulation of electron waves propagating in graphene superlattices, by fully exploiting the compute resources of heterogeneous GPUs concurrently. As old GPUs start failing and new ones are launched in the market, we equip our labs with more recent hardware, creating a variety of distinct GPU families that have non-negligent processing power available, but sometimes unused. Here we show how to exploit them with reduced parallel programming effort of the workload distribution on heterogeneous multi-GPU systems. the speedups obtained when comparing execution against uniform workload distribution (i.e. the same workload on each GPU) range from 1.2x up to 1.8x.

关键词： Electron wave simulation Graphene superlattice Stencil computation High-performance computing Dynamic workload distribution Multi-GPU parallelization

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RVNoC: A Framework for Generating RISC-V NoC-based MPSoC 26

RVNoC: A Framework for Generating RISC-V NoC-based MPSoC

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Elmohr, Mahmoud A. Eissa, Ahmed S. Ibrahim, Moamen Khamis, Mostafa El-Ashry, Sameh Shalaby, Ahmed AbdElsalam, Mohamed El-Kharashi, M. Watheq Alexandria Univ Dept Commun & Elect Fac Engn Alexandria Egypt Univ Oulu Ctr Ubiquitous Comp Oulu Finland Mentor Graph Corp Cairo Egypt Ain Shams Univ Dept Comp & Syst Engn Cairo Egypt Benha Univ Fac Comp & Informat Dept Comp Sci Banha Egypt

ISBN: (纸本)9781538649756

With the increase in the number of cores embedded on a chip;the main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. the proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 mu W/MHz power consumption.

关键词： Multiprocessor System-on-Chip (MPSoC) network-on-Chip (NoC) RISC-V System-on-Chip (SoC)

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12th International conference on Cloud Computing, CLOUD 2019 held as part of the Services conference Federation, SCF 2019

12th International Conference on Cloud Computing, CLOUD 2019...

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12th International conference on Cloud Computing, CLOUD 2019 held as part of the Services conference Federation, SCF 2019

ISBN: (纸本)9783030235017

the proceedings contain 24 papers. the special focus in this conference is on Cloud Computing. the topics include: Exploiting the spam correlations in scalable online social spam detection;dynamic network anomaly detection system by using deep learning techniques;heterogeneity-aware data placement in hybrid clouds;towards automated configuration of cloud storage gateways: A data driven approach;the case for physical memory pools: A vision paper;a parallel algorithm for bayesian text classification based on noise elimination and dimension reduction in spark computing environment;on the optimal number of computational resources in MapReduce;class indistinguishability for outsourcing equality conjunction search;a hybrid approach for synchronizing clocks in distributed systems;a Method and tool for automated induction of relations from quantitative performance logs;JCallGraph: Tracing microservices in very large scale container cloud platforms;an overview of cloud computing testing research;a robust multi-terminal support method based on tele-immersion multimedia technology;CMonitor: A monitoring and alarming platform for container-based clouds;CPR: Client-side processing of range predicates;systematic construction, execution, and reproduction of complex performance benchmarks;multiple workflow scheduling with offloading tasks to edge cloud;min-edge P-cycles: An efficient approach for computing P-cycles in optical data center networks;toward accurate and efficient emulation of public blockchains in the cloud;Teleportation of VM disk images over WAN;live migration of virtual machines in openstack: A perspective from reliability evaluation;an approach to failure prediction in cluster by self-updating cause-and-effect graph.

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Exploring Energy Efficiency Model Generalization on Multicore Embedded Platforms 26

Exploring Energy Efficiency Model Generalization on Multicor...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Rexha, Hergys Lafond, Sebastien Abo Akad Univ Fac Sci & Engn Turku Finland

ISBN: (纸本)9781538649756

In this paper we investigate the relation between energy efficiency model and workload type executed in modern embedded architectures. From the energy efficiency model obtained in our previous work we select a few configuration points to verify that the prediction in terms of relative energy efficiency is maintained through different workload scenarios. A configuration point is defined as a set of platform tunable metrics, such as DVFS point, DPM level and utilization rate. As workloads, we use a combination of synthetic generators and real world applications from the embedded domain. In our experiments we use two different architectures for testing the model generality, which provide examples of real systems. First we have a comparison of the efficiency obtained by the two architecturally different chips (ARM and INTEL) in different configuration points and different workload scenarios. Second we try to explain the different results through the thermal management done by the two different chips. At the end we show that only in the case of workloads highly composed by integer instructions the results from the two architectures converge and show the need for a specific model trained with integer operations.

关键词： Computer architecture Temperature measurement Power dissipation Load modeling Benchmark testing Energy consumption Brain modeling

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Shrink or Substitute: Handling Process Failures in HPC Systems using In-situ Recovery 26

Shrink or Substitute: Handling Process Failures in HPC Syste...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Ashraf, Rizwan A. Hukerikar, Saurabh Engelmann, Christian Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN 37831 USA

ISBN: (纸本)9781538649756

Efficient utilization of today's high-performance computing (HPC) systems with complex hardware and software components requires that the HPC applications are designed to tolerate process failures at runtime. With low mean-time-to-failure (MTTF) of current and future HPC systems, long running simulations on these systems require capabilities for gracefully handling process failures by the applications themselves. In this paper, we explore the use of fault tolerance extensions to Message Passing Interface (MPI) called user-level failure mitigation (ULFM) for handling process failures without the need to discard the progress made by the application. We explore two alternative recovery strategies, which use ULFM along with application-driven in-memory checkpointing. In the first case, the application is recovered with only the surviving processes, and in the second case, spares are used to replace the failed processes, such that the original configuration of the application is restored. Our experimental results demonstrate that graceful degradation is a viable alternative for recovery in environments where spares may not be available.

关键词： Fault Tolerance Process Failures Checkpoint/Restart Message Passing Interface Recovery

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Scalable Mapping of Streaming Applications onto MPSoCs using Optimistic Mixed Integer Linear Programming 26

Scalable Mapping of Streaming Applications onto MPSoCs using...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Gayen, Neela Kelly, Wayne Tang, Maolin Ax, Johannes Flasskamp, Martin Klarhorst, Christian Jungeblut, thorsten Queensland Univ Technol Fac Sci & Engn Brisbane Qld Australia Bielefeld Univ CITEC Cognitron & Sensor Syst Grp Bielefeld Germany

ISBN: (纸本)9781538649756

Embedded streaming applications are facing increasingly demanding performance requirements in terms of throughput. A common mechanism for providing high compute power with a low energy budget is to use a very large number of low-power cores, often in the form of a Massively parallel System on Chip (MPSoC). the challenge with programming such massively parallel systems is deciding how to optimally map the computation to individual cores for maximizing throughput. In this work we present an automatic parallelizing compiler for the StreamIt programming language that efficiently and effectively maps computation to individual cores. the compiler must be both effective, meaning that it does a good job of optimizing for throughput;but also efficient, in that the time taken to find such a mapping must scale well as the number of cores and size of the Stream program increases. We improve on previous work that used Integer Linear Programming (ILP) to map StreamIT programs to multicore systems by formulating the mapping problem in a different way using mostly real rather than integer variables. Using so called Mixed Integer Linear Programming (MILP) dramatically reduces the cost compared to standard ILP. this alternative formulation creates what we call an optimistic solution that we then need to adjust slightly to obtain a final feasible solution. We show that this new approach is always close, if not better in terms of effectiveness, while being dramatically better in terms of scalability and efficiency.

关键词： streamIt integer linear programming scalable mapping

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CSSMT: Compiler based Software Simultaneous Multithreading (SMT) 26

CSSMT: Compiler based Software Simultaneous Multithreading (...

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26th euromicro International conference on parallel, distributed, and network-based processing (PDP)

作者： Chen, Yuanfang Shi, Qingchuan Li, Xiaoming Univ Delaware Elect & Comp Engn Dept Newark DE 19716 USA Adv Micro Devices Inc Santa Cruz CA USA

ISBN: (纸本)9781538649756

Simultaneous multithreading (SMT) is a unique computer architecture feature to increase the pipeline utilization and therefore, increase the instruction throughput. It improves instruction level throughput by simultaneously filling both vertical and horizontal super-scalar pipeline slots that are left unfilled by native threads. So far SMT has been implemented in hardware. However, hardware SMT implementations have its limitations. First, it is complex and expensive to implement-only higher-end processors are equipped with it even though lower-end processors have same pipeline design as the higher-end variants and might also benefit from it. SMT also introduces great power/energy and area overheads. Moreover, being a hardware feature, SMT is limited by the range and depth of instruction analysis that it can afford at execution time, therefore it is unlikely to benefit from high-level software knowledge about instruction mix and might lose many improvement opportunities. In this paper, we address the limitation of the hardware-based SMT and introduce CSSMT: Compiler based Software Simultaneous Multithreading (SMT). the main contribution of CSSMT is that it exploits high-level program profiles to purposefully "re-mix" instructions from multiple programs to better fill vertical and horizontal super-scalar pipeline slots so that the overall throughput is improved. Furthermore, CSSMT is a software-transformation technique that enables SMT at software level during compilation time. therefore, it can help overcome the limitation of the hardware-based SMT implementation and is more portable. We test CSSMT with programs from SPEC2006 and NAS benchmarks and achieve up to 12% speedup of execution time (30.7% improvement in terms of multi-program throughput).

关键词： Compiler LLVM Simultaneous multithreading SMT

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