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检索条件"任意字段=12th Euromicro Conference on Parallel, Distributed and Network-Based Processing"

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A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures 25

A Rapid Data Communication Exploration Tool for Hybrid CPU-F...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Makni, Mariem Niar, Smail Baklouti, Mouna Zhong, Guanwen Mitra, Tulika Abid, Mohamed Univ Valenciennes LAMIH Valenciennes France Natl Engn Sch Sfax Sfax Tunisia Natl Univ Singapore Singapore Singapore

ISBN: (纸本)9781509060580

Modern System-on-Chip (SoC) designs face many challenges. Choosing the best communication protocol among the different processing nodes is one of the most important design decisions. On-chip communication architectures can have a significant impact on the performance of SoC designs. However, in most of the existing design tools, only the computation cost is accurately estimated. To address this challenge, we present a high-level analytical tool to estimate the data communication cost for hybrid CPU-FPGA architectures. the proposed model allows to estimate, rapidly and accurately, both computation and communication cost of applications containing multiple nested loops. this paper also explores the benefits of applying various optimization pragmas including dataflow and loop pipelining, at the compilation phase. Experimental results show that the proposed model provides accurate data communication estimation for hybrid CPUFPGA architectures.

关键词： Kernel Data communication Estimation Computational modeling Pipeline processing Analytical models Field programmable gate arrays

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parallel Satisfiability Solver based on Hybrid Partitioning Method 25

Parallel Satisfiability Solver Based on Hybrid Partitioning ...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Menouer, Tarek Baarir, Souheib Paris Ouest Nanterre La Def Univ Lab LIP6 CNRS UMR 7606 Paris France LRDE Lab Le Kremlin Bicetre France

ISBN: (纸本)9781509060580

this paper presents a hybrid partitioning method used to improve the performance of solving a Satisfiability ( SAT) problem. the principle of our approach consist firstly to apply a static partitioning to decompose the search tree in finite set of disjoint sub-trees, than assign each sub-tree to one computing core. However it is not easy to choose the relevant branching variables to partition the search tree. We propose in this context to partition the search tree according to the variables that occur more frequently then others. the advantage of this method is that it gives a good disjoint sub-trees. However, the drawback is the imbalance load between all computing cores of the system. To overcome this drawback, we propose as novelty to extend the static partitioning by combining with a new dynamic partitioning that assures a good load balancing between cores. Each time a new waiting core is detected, the dynamic partitioning selects automatically using an estimation function the computing core which has the most work to do in order to partition dynamically its sub-tree in two parts. It keeps one part and gives the second part to the waiting core. Preliminary result show that a good speedup is achieved using our hybrid method.

关键词： parallelism Satisfiability Load balancing Scheduling

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CSSMT: Compiler based Software Simultaneous Multithreading (SMT)

CSSMT: Compiler based Software Simultaneous Multithreading (...

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euromicro International conference on parallel, distributed and network-based processing

作者： Yuanfang Chen Qingchuan Shi Xiaoming Li Electrical and Computer Engineering Department University of Delaware Advanced Micro Devices Inc Santa Clara CA US

Simultaneous multithreading (SMT) is a unique computer architecture feature to increase the pipeline utilization and therefore, increase the instruction throughput. It improves instruction level throughput by simultaneously filling both vertical and horizontal super-scalar pipeline slots that are left unfilled by native threads. So far SMT has been implemented in hardware. However, hardware SMT implementations have its limitations. First, it is complex and expensive to implement - only higher-end processors are equipped with it even though lower-end processors have same pipeline design as the higher-end variants and might also benefit from it. SMT also introduces great power/energy and area overheads. Moreover, being a hardware feature, SMT is limited by the range and depth of instruction analysis that it can afford at execution time, therefore it is unlikely to benefit from high-level software knowledge about instruction mix and might lose many improvement opportunities. In this paper, we address the limitation of the hardware-based SMT and introduce CSSMT: Compiler based Software Simultaneous Multithreading (SMT). the main contribution of CSSMT is that it exploits high-level program profiles to purposefully "re-mix" instructions from multiple programs to better fill vertical and horizontal super-scalar pipeline slots so that the overall throughput is improved. Furthermore, CSSMT is a software-transformation technique that enables SMT at software level during compilation time. therefore, it can help overcome the limitation of the hardware-based SMT implementation and is more portable. We test CSSMT with programs from SPEC2006 and NAS benchmarks and achieve up to 12% speedup of execution time (30.7% improvement in terms of multi-program throughput).

关键词： Pipelines Standards throughput Hardware Instruction sets Merging

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Efficient Bottleneck Detection in Stream Process System Using Fuzzy Logic Model 25

Efficient Bottleneck Detection in Stream Process System Usin...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Zhai, Yanlong Xu, Wu Beijing Inst Technol Sch Comp Sci Beijing Engn Res Ctr Mass Language Informat Proc Beijing Peoples R China

ISBN: (纸本)9781509060580

Big Data has shown lots of potential in numerous domain and becomes one of the emerging technologies that are bringing revolution in some real world industry. It has the power to provide insights into the unseen aspects of immense volume of data. Some applications are processing the data using a store-then-process paradigm, whereas other applications, like telecommunications and large-scale sensor networks, have to analyze continuous data flow online. Stream processing Engines(SPEs) are designed to support applications which require timely analysis of high volume data streams. the dynamic nature of data stream requires SPEs to have high scalability. However, current SPEs mostly adopt a static configuration and can not scale out/in flexibly along with the changing of the data stream. In this paper, we proposed a fuzzy logic based runtime bottleneck operator detection approach to improve the scalability of SPEs by providing resources in the cloud environment. Our experimental results show that the fuzzy logic component developed in this work could detect bottleneck operators efficiently. Compared with other bottleneck detection methods, the decision results generated by our approach is more flexible and will not scale out/in the system when the workload change instantly.

关键词： Stream processing System Fuzzy Logic Scalability Big Data

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network-Aware VM Migration Heuristics for Improving the SLA Violation of Multi-tier Web Applications in the Cloud 25

Network-Aware VM Migration Heuristics for Improving the SLA ...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Borhani, Amir Hossein Hung, Terence Lee, Bu-sung Qin, Zheng Bagheri, Zahra Nanyang Technol Univ Sch Comp Sci & Engn Singapore 639798 Singapore Rolls Royce Pte Ltd Singapore Singapore IHPC Singapore 138632 Singapore Univ Isfahan Fac Comp Engn Esfahan Iran

ISBN: (纸本)9781509060580

the virtualization technology enables multi-tier web application to be hosted in the Cloud. But the Service Level Agreement (SLA) is likely to be negatively affected when the network traffic is high as they may quickly overload the data center network and increase the response time of the system. Additionally, data centers experience high operational costs due to their considerable amount of energy consumption. the Virtual Machine (VM) technology and VM migration have been widely utilized to deal with such challenges. In this paper, we present design and implementation of an adaptive network-aware VM migration algorithm. the VM and target selection policies are based on the steady state network traffic in the system to minimize the negative effect of migration on other flows on the network. Moreover, we address the high energy consumption of the data center by employing an energy-aware VM placement algorithm. the effectiveness of our proposed VM migration algorithm is evaluated by extensive simulations in CloudSim using real workload traces. We compared two overloading detection policies in our experiments. the results show that our algorithm is able to improve the SLA violation (SLAV) and energy consumption up to 73% and 81%, respectively.

关键词： Resource Management Energy Efficient and Management Service Level Agreement Multi-tier Web Applications network-Aware VM Migration Energy-Aware VM Migration

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A GPU Implemented 3F Cellular Automata-based Model for a 2D Evacuation Simulation Pattern 25

A GPU Implemented 3F Cellular Automata-based Model for a 2D ...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Koumis, Isaac Georgoudas, Ioakeim G. Sirakoulis, Georgios Ch. Trunfio, Giuseppe A. Was, Jaroslaw Democritus Univ Thrace Dept Elect & Comp Engn Xanthi Greece Univ Sassari Dept Architecture Planning & Design Alghero Italy AGH Univ Sci & Technol Dept Appl Comp Sci Krakow Poland

ISBN: (纸本)9781509060580

this study presents the principles of a Cellular Automata (CA) based model that incorporates an enhanced version of the floor-field model targeting the fire spreading representation, thus called fire-floor-field (3F). the aim of the model is to simulate evacuation processes fast and reliably, in order to act as the core module of a near real-time effective anticipation system. To this direction, the model takes advantage of massive parallelism, an inherent feature of CA, by employing the efficient response of the floor field model and the accurate computational reproduction of fire-front evolution. Furthermore, a Graphic processing Unit (GPU) based implementation of the proposed model is presented. Such a realisation aims at further speeding up the response of the model and it reinforces the fundamental goal of rapid activation. the model is validated quantitatively and qualitatively by being applied in the case of the two-dimensional (2D) simulated evacuation of the Building B, of the Department of Electrical and Computer Engineering, Democritus University of thrace, under fire spreading conditions.

关键词： cellular automata modeling evacuation simulation floor-field fire spreading graphic processing unit

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Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs 25

Buffer-Aware Analysis for Worst-Case Traversal Time of Real-...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Liu, Meng Becker, Matthias Behnam, Moris Nolte, thomas Malardalen Univ Vasteras Sweden

ISBN: (纸本)9781509060580

network-on-Chip (NoC) is a communication subsystem which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.

关键词： Real-time systems Timing Computer architecture Program processors Calculus System-on-chip Time factors

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Efficient Regional Congestion Awareness(ERCA) for Load Balance with Aggregated Congestion Information 25

Efficient Regional Congestion Awareness(ERCA) for Load Balan...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Xu, Sheng Wu, Jie Fu, Binzhang Chen, Mingyu Zhang, Lixin Chinese Acad Sci ICT State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781509060580

In this paper, we propose Efficient Regional Congestion Awareness(ERCA), a novel adaptive routing technique which utilizes both local and non-local/aggregated congestion information to estimate network congestion. To reduce the interference caused by the noises of the congestion information, two optimizations are performed: first, to minimize the noises of the congestion information, ERCA only considers the congestion status of the links adjacent to the nodes defined from current to the corresponding boundary;second, to minimize the influence of the noises, ERCA exploits dynamic instead of static weights to evaluate port's congestion. Furthermore, ERCA uses one wire per dimension direction or quadrant to transmit congestion information between two adjacent nodes, so the wiring overhead of ERCA is minimal. Compared with the DBAR, ERCA can maximally improve the saturation throughput by 11.7% and averagely improve the saturation throughput by 6.02%.

关键词： network-on-Chip regional congestion awareness adaptive routing algorithm

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An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering 25

An FPGA-Based In-NIC Cache Approach for Lazy Learning Outlie...

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25th euromicro International conference on parallel, distributed and network-based processing (PDP)

作者： Hayashi, Ami Matsutani, Hiroki Keio Univ Dept ICS Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan

ISBN: (纸本)9781509060580

As data sets grow rapidly in size and the number, an outlier detection that filters unnecessary normal information becomes important. In this paper, we propose to move the outlier detection from an application layer to a NIC (network Interface Card). Only anomalous items or events are delivered for a network protocol stack and the other packets are discarded at the NIC. the demands for storage and computation costs at a host are thus drastically reduced. We employ lazy learning algorithms for the outlier detection, because they can he applied to complex reference data including different clusters. However, it is challenging to offload the lazy learning to NIC hardware because of high computational cost and huge reference data. In this paper, we propose to cache only a frequently-accessed portion of reference data in the NIC. this idea can be applied to lazy learning algorithms in general. LOF (Local Outlier Factor) and KNN (K-Nearest Neighbor) are thus implemented on an FPGA (Field Programmable Gate Arrays) based NIC. Simulation results of the proposed system using LOF with 100,000 reference data show that 45% to 90% of queries are hit to the proposed cache and filtered at the MC. the results are corresponding to 1.82x to 10x throughput improvements on the outlier filtering compared to that of a software-based execution.

关键词： Field programmable gate arrays Detection algorithms Servers Mathematical model Protocols Hardware Acceleration

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Performance Evaluation of DBN Learning on Intel Multi- and Manycore Architectures 12th

Performance Evaluation of DBN Learning on Intel Multi- and M...

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12th International conference on parallel processing and Applied Mathematics (PPAM)

作者： Olas, Tomasz Mleczko, Wojciech K. Wozniak, Marcin Nowicki, Robert K. Gepner, Pawel Czestochowa Tech Univ Inst Comp & Informat Sci Dabrowskiego 69 PL-42201 Czestochowa Poland Czestochowa Tech Univ Inst Computat Intelligence Armii Krajowej 36 PL-42201 Czestochowa Poland Intel Corp Santa Clara CA USA

ISBN: (纸本)9783319780245;9783319780238

In our previous papers [12,13], we proposed the parallel realization of the Deep Belief network (DBN). this research confirmed the potential usefulness of the first generation of the Intel MIC architecture for implementing DBN and similar algorithms. In this work, we investigate how the Intel MIC and CPU platforms can be applied to implement efficiently the complete learning process using DBNs with layers corresponding to the Restricted Boltzman Machines. the focus is on the new generation of Intel MIC devices known as Knights Landing. Unlike the previous generation, called Knights Corner, they are delivered not as coprocessors, but as standalone processors. the learning procedure is based on the matrix approach, where learning samples are grouped into packages, and represented as matrices. We study the possible ways of improving the performance taking into account features of the Knights Landing architecture, and parameters of the learning algorithm. In particular, the influence of the package size on the accuracy of learning, as well as on the performance of computations are investigated using conventional CPU and Intel Xeon Phi. the performance advantages of Knights Landing over Knights Corner are presented and discussed.

关键词： Deep Belief network Restricted Boltzman Machine Multi- and manycore architectures OpenMP Intel Xeon Phi Knights Landing

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