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检索条件"任意字段=12th Euromicro Conference on Parallel, Distributed and Network-Based Processing"

共 1250 条记录，以下是411-420 订阅

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NoSQL Database Record Versions processing Model

NoSQL Database Record Versions Processing Model

引用

euromicro conference on parallel, distributed and network-based processing

作者： Aleksey Burdakov Uriy Grigorev Eugene Ttsviashchenko Andrey Ploutenko Bauman Moscow State Technical University BMSTU Moscow Russia Amur State University AmSU Blagoveschensk Russia

ISBN: (纸本)9781509060597

this article reviews record versions processing (reconciliation). It provides an algorithm for NoSQL database record versions management. It develops a record versions reconciliation model that is simultaneously updated by multiple users. the model estimates record versions reconciliation time and the number of versions simultaneously stored in a database. based on the modeling results a designer can provide recommendations on the maximum number of users (or applications) simultaneously working with one document (database record). this is important in case there are limitations imposed on the document reconciliation time. It describes preparation and execution of experiments in a cloud, for model adequacy analysis.

关键词： Algorithm design and analysis Clocks Analytical models parallel processing Mathematical model

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Asynchronous Power Flow on Graphic processing Units

Asynchronous Power Flow on Graphic Processing Units

引用

euromicro conference on parallel, distributed and network-based processing

作者： Manuel Marin David Defour Federico Milano Université de Liège Institut Montefiore Liège Belgium Université de Perpignan Via Domitia LIRMM France School of Electrical Electronic and Communications Engineering of the University College Dublin Dublin Ireland

ISBN: (纸本)9781509060597

Asynchronous iterations can be used to implement fixed-point methods such as Jacobi and Gauss-Seidel on parallel computers with high synchronization costs. However, they are rarely considered in practice due to the slow convergence rate. this paper describes an implementation on GPUs of a novel Power Flow analysis model using asynchronous iterations. We present our model for the solution of the Power Flow analysis problem, prove its convergence and evaluate its performance for a GPU execution.

关键词： Convergence Synchronization Graphics processing units Instruction sets Delays Power systems Analytical models

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TORMENT OpenACC2016: A Benchmarking Tool for OpenACC Compilers

TORMENT OpenACC2016: A Benchmarking Tool for OpenACC Compile...

引用

euromicro conference on parallel, distributed and network-based processing

作者： Daniel Barba Arturo Gonzalez-Escribano Diego R. Llanos Dpto. de Informática Universidad de Valladolid Valladolid Spain

ISBN: (纸本)9781509060597

OpenACC is a parallel programming model for hardware accelerators, such as GPUs or Xeon Phi, which has been in development for several years by now. During this time, different compilers have appeared, both commercial and open source, which are still on development stage. Due to the fact that both the OpenACC standard and its implementations are relatively recent, we propose a benchmark suite specifically designed to check the performance of the OpenACC features in the code generated by different compilers on different architectures. Our benchmark suite is named TORMENT OpenACC2016. Along with this tool we have developed an adequate metric for the comparison of performance among different machine-compiler pairs which we have named TORMENT ACC2016 Score. the version 1 of TORMENT OpenACC2016 presented in this paper, contains six benchmarks, and is available online.

关键词： Benchmark testing Standards Measurement Graphics processing units Writing Performance analysis Proposals

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Transforming Procedural Code for Streaming Environments

Transforming Procedural Code for Streaming Environments

引用

euromicro conference on parallel, distributed and network-based processing

作者： Michal Brabec David Bednárek Department of Software Engineering Charles University Prague Czech Republic

ISBN: (纸本)9781509060597

Streaming environments and similar parallel platforms are widely used in image, signal, or general data processing as a means of achieving high performance. Unfortunately, they are often associated with specific programming languages and, thus, hardly accessible for non-experts. In this paper, we present a framework for transformation of a C# procedural code to a Hybrid Flow Graph - a novel intermediate code which employs the streaming paradigm and can be further converted into a streaming application. this approach will allow creating streaming applications or their parts using a widely known imperative language instead of an intricate language specific to streaming. In this paper, we focus on the transformation of control flow which represents the main difference between procedural code, driven by control flow constructs, and streaming environments, driven by data. Since the use of a streaming platform automatically enables parallelism and vectorization, we were able to demonstrate that the streaming applications generated by our method may outperform their original C# implementation.

关键词： flow graphs parallel processing programming languages Flowcharts Computer Programming Languages Streaming parallel processing (COMPUTERS) image signal Codes

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Compiler-Enhanced Reliability for network-on-Chip Architectures

Compiler-Enhanced Reliability for Network-on-Chip Architectu...

引用

euromicro conference on parallel, distributed and network-based processing

作者： Muhammad Aditya Sasongko Haluk Rahmi Topcuoglu Sanem Arslan Mahmut Taylan Kandemir Computer Engineering Department Marmara University Istanbul Turkey Dept. of Computer Science and Engineering University Park PA USA

ISBN: (纸本)9781509060597

the small feature sizes in current networks-on-chip (NoCs) have increased the importance of reliability. However, existing fault tolerance schemes incur costs in terms of performance and power consumption which can be over-burdening. In order to tackle the reliability problem in NoCs while minimizing the performance and energy costs, a compiler-enhanced reliability scheme is introduced in this paper which assigns extra protection only to data transmissions in NoC which are considered critical. the experimental study validates that our scheme yields almost equal level of fault tolerance for critical data transmissions with the scheme that protects all packet transmissions indiscriminately. Our scheme is also shown to have better performance by approximately 7% than the conservative scheme for the tested criticality annotation.

关键词： Fault tolerance Fault tolerant systems Routing Computer network reliability Hardware Arrays

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Efficient Fast Convolution Architectures for Convolutional Neural network 12

Efficient Fast Convolution Architectures for Convolutional N...

引用

2017 IEEE 12th International conference on ASIC

作者： Weihong Xu Zhongfeng Wang Xiaohu You Chuan Zhang Lab of Efficient Architectures for Digital-communication and Signal-processing(LEADS) National Mobile Communications Research Laboratory Southeast University School of Electronic Science and Engineering Nanjing University

ISBN: (纸本)9781509066261;9781509066254

Due to the world-wide interests on artificial intelligence,many acceleration architectures for convolutional neural network(CNN) have been proposed ***,few of them focus on reducing convolution computation *** this paper,we first present fast convolution algorithm and its matrix *** based on the fast convolution algorithm,a fully parallel architecture with high throughput is *** further increase efficiency and reduce computation redundancy,output data reuse scheme corresponding to CNN is also considered by introducing affordable adders and *** hardware implementation and complexity comparison are conducted among different convolution *** results on Zynq XC7 Z045 platform demonstrate the effectiveness of proposed fast convolution architectures in the reduction of *** to conventional 2-D convolver,our 3-parallel fast convolution filter reduces 28% hardware resources and improves throughput by 17%.After deploying data reuse scheme,our fast convolution architecture is 10.56× faster.

关键词： Fast convolution parallel processing data reuse hardware reconfigurability convolutional neural network(CNN)

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Modelling Low Power Compute Clusters for Cloud Simulation

Modelling Low Power Compute Clusters for Cloud Simulation

引用

euromicro conference on parallel, distributed and network-based processing

作者： Gabor Kecskemeti Wajdi Hajji Fung Po Tso Department of Computer Science Liverpool John Moores University Liverpool United Kingdom

ISBN: (纸本)9781509060597

In order to minimise their energy use, data centre operators are constantly exploring new ways to construct computing infrastructures. As low power CPUs, exemplified by ARM-based devices, are becoming increasingly popular, there is a growing trend for the large scale deployment of low power servers in data centres. For example, recent research has shown promising results on constructing small scale data centres using Raspberry Pi (RPi) single-board computers as their building blocks. To enable larger scale experimentation and feasibility studies, cloud simulators could be utilised. Unfortunately, state-of-the-art simulators often need significant modification to include such low power devices as core data centre components. In this paper, we introduce models and extensions to estimate the behaviour of these new components in the DISSECT-CF cloud computing simulator. We show that how a RPi based cloud could be simulated with the use of the new models. We evaluate the precision and behaviour of the implemented models using a Hadoop-based application scenario executed both in real life and simulated clouds.

关键词： Cloud computing Economic indicators Computational modeling Central processing Unit Containers Data models Sparks

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Softening Up the network for Scientific Applications

Softening Up the Network for Scientific Applications

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euromicro conference on parallel, distributed and network-based processing

作者： Celio Trois Luis C. E. de Bona Marcos D. Del Fabro Magnos Martinello Sarvesh Bidkar Reza Nejabati Dimitra Simeonidou Federal University of Parana Curitiba Brazil Universidade Federal do Parana Curitiba PR BR Federal University of Espirito Santo Espirito Santo Brazil High- Performance Networks Group University of Bristol Bristol United Kingdom High-Performance Networks Group University of Bristol Bristol Bristol GB

ISBN: (纸本)9781509060597

Scientific applications demand huge computational power connected through fast networks. they are developed using parallel kernel methods, usually implemented with the Message Passing Interface (MPI), presenting well-behaved communication patterns across computing nodes. the current network technologies do not allow defining traffic forwarding policies considering the different application traffic, resulting in an unbalanced load on the network links. Moreover, the devices are not concerned if the traffic is latency-sensitive or bandwidth-intensive. To handle this, we present NetSA, a framework exploiting the communication patterns of scientific applications, considering latency and bandwidth constraints, as the key logic for evenly placing the application flows on the network available paths. through NetSA, the scientific application developer can easily modify the network behavior to best fit the application communication requirements. We have performed experiments for optimizing the MPI communication primitives and applied our solution to speed up scientific applications, obtaining an execution time reduction up to 27%.

关键词： Bandwidth network topology Programming Topology Protocols Switches Kernel

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High Performant Simulations of Cerebellar Golgi Cells Activity

High Performant Simulations of Cerebellar Golgi Cells Activi...

引用

euromicro conference on parallel, distributed and network-based processing

作者： Giordana Florimbi Emanuele Torti Giovanni Danese Francesco Leporati Department of Electrical Computer and Biomedical Engineering University of Pavia Pavia Italy

ISBN: (纸本)9781509060597

the use of High Performance Computing (HPC) technologies is gaining interest in the field of neuronal activity simulations. In fact, scientists' main goal is to understand and reproduce cells behavior in a realistic way. this will allow undertaking in silico experiments, instead of in vivo ones, to test new medicines, to study cerebral pathologies and to discover innovative therapies. To this aim, two main requirements are necessary: neurons have to be described by realistic models and their simulation hopefully have to satisfy the real-time constraint. this last property is very hard to accommodate because models used in these works are very heavy from the computational point of view. For this reason, authors decide to exploit Graphic processing Unit (GPU) technology to simulate the cellular activity of Golgi cells, which constitute the cerebellar cortex. this paper describes an efficient Golgi cell activity simulation performed using NVIDIA GPUs. Results show that simulation times are reduced from 41 hours to about 2 hours when simulating 400'000 different cells.

关键词： Computational modeling Neurons Mathematical model Biological system modeling Graphics processing units Brain modeling Integrated circuit modeling

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An Experimental Study on Deep Learning based on Different Hardware Configurations

An Experimental Study on Deep Learning Based on Different Ha...

引用

12th International conference on networking, Architecture, and Storage (NAS)

作者： Li, Jingjun Zhang, Chen Cao, Qiang Qi, Chuanyi Huang, Jianzhong Xie, Changsheng Huazhong Univ Sci & Technol Minist Educ China Key Lab Informat Storage Syst Wuhan Natl Lab Optoelect Wuhan 430074 Hubei Peoples R China

ISBN: (纸本)9781538634868

Deep learning has exhibited high accuracy and applicability in machine learning field recently, by consuming tremendous computational resources processing massive data. To improve the performance of deep learning, GPUs have been introduced to accelerate the training phase. the complex data processing infrastructure demands high-efficient collaboration among underlying hardware components, such as CPU, GPU, memory, and storage devices. Unfortunately, few work has presented a systematic analysis about the impact of hardware configurations on the overall performance of deep learning. In this paper, we aim to make an experimental study on a standalone system to evaluate how various hardware configurations affect the overall performance of deep learning. We conducted a series of experiments using varied configurations on storage devices, main memory, CPU, and GPU to observe the overall performance quantitatively. based on analyzing these results, we found that the performance greatly relies on the hardware configurations. Specifically, the computation is still the primary bottleneck as double GPUs and triple GPUs shorten the execution time by 44% and 59% respectively. Besides, both CPU frequency and storage subsystem can significantly affect running time while the memory size has no obvious effect on the running time for training neural network models. We believe our experimental results can help shed light on further optimizing the performance of deep learning in computer systems.

关键词： Performance evaluation Graphics processing units Training Hardware Machine learning Neural networks Arrays

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